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SuperHTM RISC engine SH7020 and SH7021 HD6437020, HD6477021, HD6437021, HD6417021
Hardware Manual
ADE-602-074B Rev. 3.0 3/7/03 Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Introduction
The SH7020 and SH7021 are part of a new generation of reduced instruction-set computer-type (RISC) microcomputers that integrate RISC-type CPUs and the peripheral functions required for system configuration onto a single chip to achieve high-performance operations processing. They can operate in a power-down state, which is an essential feature for portable equipment. The SH7020 and SH7021 CPUs have RISC-type instruction sets. Basic instructions can be executed in a single clock cycle, which strikingly improves instruction execution speed. The SH7020 and SH7021 include peripheral functions such as large-capacity ROM (PROM or masked ROM), RAM, a direct memory access controller (DMAC), timers, a serial communication interface (SCI), an interrupt controller (INTC), and I/O ports. These on-chip elements enable users to construct systems with the fewest possible components. External memory access support functions enable direct connection to SRAM and DRAM. without the use of glue logics. This Hardware Manual describes in detail the hardware functions of the SH7020 and SH7021. For information on the instructions, please refer to the Programming Manual.
Related Manuals
SH7000 Series Instructions "SH-1/SH-2/SH-DSP Programming Manual" For development support tools, contact your Hitachi sales office.
Organization of This Manual
Table 1 describes how this manual is organized. Figure 1 shows the relationships between the Sections within this manual.
Table 1 Manual Organization Category Overview CPU Section Title 1. 2. Overview CPU Abbreviation -- CPU Contents Features, internal block diagram, pin layout, pin functions Register configuration, data structure. instruction features, instruction types, instruction lists MCU mode, PROM mode Resets, address errors, interrupts, trap instructions, illegal instructions NMI interrupts, user break interrupts, IRQ interrupts, on-chip module interrupts Break address and break bus cycles selection Crystal pulse generator, duty correction circuit Division of memory space, DRAM interface, refresh, wait state control, parity control Auto request, external request, on-chip peripheral module request, cycle steal mode, burst mode Waveform output mode, input capture function, counter clear function, buffer operation, PWM mode, complementary PWM mode, reset synchronized mode, synchronized operation, phase counting mode, compare match output mode Compare match output triggers, non-overlap operation Watchdog timer mode, interval timer mode Asynchronous mode, clock synchronous mode, multiprocessor communication function
Operating Modes Internal Modules
3. 4. 5. 6.
Operating Modes Exception Processing Interrupt Controller User Break Controller Clock Pulse Generator Bus State Controller Direct Memory Access Controller
-- -- INTC UBC CPG BSC DMAC
Clock Buses
7. 8. 9.
Timers
10. 16-Bit IntegratedTimer Pulse Unit
ITU
11. Programmable Timing Pattern Controller 12. Watchdog Timer Data Processing 13. Serial Communication Interface
TPC
WDT SCI
Table 1 Manual Organization (cont) Category Pins Section Title 14. Pin Function Controller 15. Parallel I/O Ports Memory 16. ROM 17. RAM Power-Down States Electrical Characteristics 18. Power-Down States 19. Electrical Characteristics Abbreviation PFC I/O ROM RAM -- -- Contents Pin function selection I/O port On-chip ROM On-chip RAM Sleep mode, standby mode Absolute maximum ratings, AC characteristics, DC characteristics, operation timing
1. Overview 3. Operating modes 2. CPU On-chip modules 4. Exception processing 5. Interrupt controller (INTC) 6. User break controller (UBC)
7. Clock pulse generator (CPG) Buses 8. Bus state controller (BC) 9. Direct memory access controller (DMAC) Timers 10. 16-bit integrated-timer pulse unit (ITU) 11. Programmable timing pattern controller (TPC) 12. Watchdog timer (WDT)
Memory 16. ROM 17. RAM Pins 14. Pin function controller (PFC) 15. Parallel I/O ports Data processing
13. Serial communication interface (SCI)
18. Power-down states 19. Electrical characteristics
Manual Organization Scheme
Addresses of On-Chip Peripheral Module Registers
The on-chip peripheral module registers are located in the on-chip peripheral module space (area 5: H'5000000-H'5FFFFFF), but since the actual register space is only 512 bytes, address bits A23-A9 are ignored. 32k shadow areas in 512 byte units that contain exactly the same contents as the actual registers are thus provided in the on-chip peripheral module space. In this manual, register addresses are specified as though the on-chip peripheral module registers were in the 512 bytes H'5FFFE00-H'5FFFFFF. Only the values of the A27-A24 and A8-A0 bits are valid; the A23-A9 bits are ignored. When H'5000000-H'50001FF is accessed, for example, the result will be the same as when H'5FFFE00-H'5FFFFFF is accessed. For more details, see Section 8.3.5, Area Description: Area 5.
Free Addresses in the On-chip Peripheral Module Space (Area 5)
Avoid reading/writing from/to the free addresses without registers in the on-chip peripheral module space (area 5: H'5000000-H'5FFFFFF).
Contents
Section 1 Overview ............................................................................................................
1.1 1.2 1.3 SH Microcomputer Features.............................................................................................. Block Diagram................................................................................................................... Pin Descriptions................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions........................................................................................................ 1.3.3 Pin Layout by Mode ............................................................................................. 1 1 7 8 8 9 13
Section 2 CPU ...................................................................................................................... 15
2.1 Register Configuration ...................................................................................................... 2.1.1 General Registers (Rn) ......................................................................................... 2.1.2 Control Registers.................................................................................................. 2.1.3 System Registers .................................................................................................. 2.1.4 Initial Values of Registers .................................................................................... Data Formats...................................................................................................................... 2.2.1 Data Format in Registers...................................................................................... 2.2.2 Data Format in Memory ....................................................................................... 2.2.3 Immediate Data Format........................................................................................ Instruction Features .............................................................................................................. 2.3.1 RISC-Type Instruction Set ................................................................................... 2.3.2 Addressing Modes................................................................................................ 2.3.3 Instruction Formats .............................................................................................. Instruction Set.................................................................................................................... 2.4.1 Instruction Set by Classification .......................................................................... 2.4.2 Operation Code Map ............................................................................................ CPU State .......................................................................................................................... 2.5.1 State Transitions ................................................................................................... 2.5.2 Power-Down State................................................................................................ 15 15 15 16 17 17 17 18 18 19 19 22 25 28 28 39 41 41 43
2.2
2.3
2.4
2.5
Section 3 Operating Modes .............................................................................................. 45
3.1 3.2 Types of Operating Modes and Their Selection................................................................ Operating Mode Descriptions............................................................................................ 3.2.1 Mode 0 (MCU Mode 0)........................................................................................ 3.2.2 Mode 1 (MCU Mode 1)........................................................................................ 3.2.3 Mode 2 (MCU Mode 2)........................................................................................ 3.2.4 Mode 7 (PROM Mode) ........................................................................................ 45 45 45 45 45 45
Section 4 Exception Processing ..................................................................................... 47
4.1 Overview............................................................................................................................ 47
4.2
4.3
4.4
4.5
4.6
4.7 4.8
4.1.1 Exception Processing Types and Priorities .......................................................... 4.1.2 Exception Processing Operation .......................................................................... 4.1.3 Exception Process Vector Table .......................................................................... Reset .................................................................................................................................. 4.2.1 Reset Types .......................................................................................................... 4.2.2 Power-On Reset.................................................................................................... 4.2.3 Manual Reset........................................................................................................ Address Errors ................................................................................................................... 4.3.1 Address Error Sources.......................................................................................... 4.3.2 Address Error Exception Processing.................................................................... Interrupts............................................................................................................................ 4.4.1 Interrupt Sources .................................................................................................. 4.4.2 Interrupt Priority Rankings................................................................................... 4.4.3 Interrupt Exception Processing ............................................................................ Instruction Exceptions ....................................................................................................... 4.5.1 Types of Instruction Exceptions........................................................................... 4.5.2 Trap Instruction .................................................................................................... 4.5.3 Illegal Slot Instruction .......................................................................................... 4.5.4 General Illegal Instructions .................................................................................. Cases in Which Exceptions Are Not Accepted ................................................................. 4.6.1 Immediately after Delayed Branch Instructions................................................... 4.6.2 Immediately after Interrupt-Disabling Instructions.............................................. Stack Status after Exception Processing............................................................................ Notes.................................................................................................................................. 4.8.1 Value of the Stack Pointer (SP)............................................................................ 4.8.2 Value of the Vector Base Register (VBR) ........................................................... 4.8.3 Address Errors that Are Caused by Stacking During Address Error Exception Processing............................................................................................
47 49 49 51 51 51 52 52 52 53 54 54 54 55 55 55 55 56 56 57 57 57 58 59 59 59 59
Section 5 Interrupt Controller (INTC) .......................................................................... 61
5.1 Overview............................................................................................................................ 61 5.1.1 Features ................................................................................................................ 61 5.1.2 Block Diagram...................................................................................................... 61 5.1.3 Pin Configuration ................................................................................................. 63 5.1.4 Registers ............................................................................................................... 63 Interrupt Sources................................................................................................................ 63 5.2.1 NMI Interrupts...................................................................................................... 64 5.2.2 User Break Interrupt ............................................................................................. 64 5.2.3 IRQ Interrupts ...................................................................................................... 64 5.2.4 On-Chip Interrupts................................................................................................ 64 5.2.5 Interrupt Exception Vectors and Priority Rankings ............................................. 65 Register Descriptions......................................................................................................... 68 5.3.1 Interrupt Priority Registers A-E (IPRA-IPRE) ................................................... 68
5.2
5.3
5.4
5.5 5.5
5.3.2 Interrupt Control Register (ICR) .......................................................................... 69 Interrupt Operation ............................................................................................................ 70 5.4.1 Interrupt Sequence................................................................................................ 70 5.4.2 Stack after Interrupt Exception Processing .......................................................... 72 Interrupt Response Time.................................................................................................... 73 Usage Notes ....................................................................................................................... 74
Section 6 User Break Controller (UBC) ...................................................................... 75
6.1 Overview............................................................................................................................ 6.1.1 Features ................................................................................................................ 6.1.2 Block Diagram...................................................................................................... 6.1.3 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 6.2.1 Break Address Registers (BAR) .......................................................................... 6.2.2 Break Address Mask Register (BAMR)............................................................... 6.2.3 Break Bus Cycle Register (BBR) ......................................................................... Operation ........................................................................................................................... 6.3.1 Flow of the User Break Operation........................................................................ 6.3.2 Break on Instruction Fetch Cycles to On-Chip Memory...................................... 6.3.3 Program Counter (PC) Value Saved in User Break Interrupt Exception Processing............................................................................................................. Setting User Break Conditions .......................................................................................... Notes.................................................................................................................................. 6.5.1 On-Chip Memory Instruction Fetch ..................................................................... 6.5.2 Instruction Fetch at Branches ............................................................................... 6.5.3 Instruction Fetch Break ........................................................................................ 75 75 75 76 77 77 78 79 81 81 84 84 84 86 86 86 87
6.2
6.3
6.4 6.5
Section 7 Clock Pulse Generator (CPG) ..................................................................... 89
7.1 7.2 Overview............................................................................................................................ 89 Clock Source...................................................................................................................... 89 7.2.1 Connecting a Crystal Resonator ........................................................................... 89 7.2.2 External Clock Input ............................................................................................ 90 Usage Notes ....................................................................................................................... 91
7.3
Section 8 Bus State Controller (BSC) ........................................................................... 93
8.1 Overview............................................................................................................................ 93 8.1.1 Features ................................................................................................................ 93 8.1.2 Block Diagram...................................................................................................... 93 8.1.3 Pin Configuration ................................................................................................. 95 8.1.4 Register Configuration ......................................................................................... 95 8.1.5 Overview of Areas................................................................................................ 96 Register Descriptions......................................................................................................... 97 8.2.1 Bus Control Register (BCR) ................................................................................ 97
8.2
8.2.2 Wait State Control Register 1 (WCR1)................................................................ 8.2.3 Wait State Control Register 2 (WCR2)................................................................ 8.2.4 Wait State Control Register 3 (WCR3)................................................................ 8.2.5 DRAM Area Control Register (DCR).................................................................. 8.2.6 Refresh Control Register (RCR) .......................................................................... 8.2.7 Refresh Timer Control/Status Register (RTCSR) ................................................ 8.2.8 Refresh Timer Counter (RTCNT) ........................................................................ 8.2.9 Refresh Time Constant Register (RTCOR).......................................................... 8.2.10 Parity Control Register (PCR).............................................................................. 8.2.11 Notes on Register Access ..................................................................................... 8.3 Address Space Subdivision................................................................................................ 8.3.1 Address Spaces and Areas.................................................................................... 8.3.2 Bus Width............................................................................................................. 8.3.3 Chip Select Signals (CS0-CS7)............................................................................ 8.3.4 Shadows................................................................................................................ 8.3.5 Area Description .................................................................................................. 8.4 Accessing External Memory Space ................................................................................... 8.4.1 Basic Timing ........................................................................................................ 8.4.2 Wait State Control ................................................................................................ 8.4.3 Byte Access Control ............................................................................................. 8.5 DRAM Interface Operation ............................................................................................... 8.5.1 DRAM Adress Multiplexing ............................................................................... 8.5.2 Basic Timing ........................................................................................................ 8.5.3 Wait State Control ................................................................................................ 8.5.4 Byte Access Control ............................................................................................. 8.5.5 DRAM Burst Mode .............................................................................................. 8.5.6 Refresh Control .................................................................................................... 8.6 Address/Data Multiplexed I/O Space Access.................................................................... 8.6.1 Basic Timing ........................................................................................................ 8.6.2 Wait State Control ................................................................................................ 8.6.3 Byte Access Control ............................................................................................. 8.7 Parity Check and Generation ............................................................................................. 8.8 Warp Mode........................................................................................................................ 8.9 Wait State Control ............................................................................................................. 8.10 Bus Arbitration .................................................................................................................. 8.10.1 The Operation of Bus Arbitration ........................................................................ 8.10.2 BACK Operation.................................................................................................. 8.11 Usage Notes ....................................................................................................................... 8.11.1 Usage Notes on Manual Reset.............................................................................. 8.11.2 Usage Notes on Parity Data Pins DPH and DPL ................................................. 8.11.3 Maximum Number of States from BREQ Input to Bus Release .........................
98 101 103 104 107 108 110 112 112 114 115 115 117 117 118 120 128 128 129 133 134 134 136 138 140 142 148 151 152 153 153 154 154 155 157 158 159 161 161 164 164
Section 9 Direct Memory Access Controller (DMAC) ......................................... 169
9.1
9.2
9.3
9.4
9.5
Overview............................................................................................................................ 9.1.1 Features ................................................................................................................ 9.1.2 Block Diagram...................................................................................................... 9.1.3 Pin Configuration ................................................................................................. 9.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 9.2.1 DMA Source Address Registers 0-3 (SAR0-SAR3) .......................................... 9.2.2 DMA Destination Address Registers 0-3 (DAR0-DAR3) .................................. 9.2.3 DMA Transfer Count Registers 0-3 (TCR0-TCR3) ........................................... 9.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3)................................... 9.2.5 DMA Operation Register (DMAOR)................................................................... Operation ........................................................................................................................... 9.3.1 DMA Transfer Flow ............................................................................................. 9.3.2 DMA Transfer Requests....................................................................................... 9.3.3 Channel Priority.................................................................................................... 9.3.4 DMA Transfer Types ........................................................................................... 9.3.5 Number of Bus Cycle States and DREQ Pin Sample Timing.............................. 9.3.6 DMA Transfer Ending Conditions ....................................................................... Examples of Use................................................................................................................ 9.4.1 DMA Transfer between On-Chip RAM and a Memory-Mapped External Device .................................................................................................... 9.4.2 Example of DMA Transfer between On-Chip SCI and External Memory.......... Cautions .............................................................................................................................
169 169 170 172 173 174 174 174 175 175 180 182 182 184 186 191 198 205 206 206 207 208
Section 10 16-Bit Integrated-Timer Pulse Unit (ITU) ............................................ 213
10.1 Overview............................................................................................................................ 10.1.1 Features ................................................................................................................ 10.1.2 Block Diagram...................................................................................................... 10.1.3 Input/Output Pins.................................................................................................. 10.1.4 Register Configuration ......................................................................................... 10.2 ITU Register Descriptions ................................................................................................. 10.2.1 Timer Start Register (TSTR)................................................................................ 10.2.2 Timer Synchro Register (TSNC).......................................................................... 10.2.3 Timer Mode Register (TMDR) ............................................................................ 10.2.4 Timer Function Control Register (TFCR)............................................................ 10.2.5 Timer Output Control Register (TOCR) .............................................................. 10.2.6 Timer Counters (TCNT)....................................................................................... 10.2.7 General Registers A and B (GRA and GRB) ....................................................... 10.2.8 Buffer Registers A and B (BRA, BRB)................................................................ 10.2.9 Timer Control Register (TCR) ............................................................................. 10.2.10 Timer I/O Control Register (TIOR) ..................................................................... 10.2.11 Timer Status Register (TSR) ................................................................................ 10.2.12 Timer Interrupt Enable Register (TIER) .............................................................. 213 213 216 221 222 224 224 226 227 230 231 232 233 234 235 237 239 240
10.3 CPU Interface .................................................................................................................... 10.3.1 16-Bit Accessible Registers.................................................................................. 10.3.2 8-Bit Accessible Registers.................................................................................... 10.4 Description of Operation ................................................................................................... 10.4.1 Overview .............................................................................................................. 10.4.2 Basic Functions .................................................................................................... 10.4.3 Synchronizing Mode ............................................................................................ 10.4.4 PWM Mode .......................................................................................................... 10.4.5 Reset-Synchronized PWM Mode ......................................................................... 10.4.6 Complementary PWM Mode................................................................................ 10.4.7 Phase Counting Mode .......................................................................................... 10.4.8 Buffer Mode ......................................................................................................... 10.4.9 ITU Output Timing .............................................................................................. 10.5 Interrupts............................................................................................................................ 10.5.1 Timing of Setting Status Flags ............................................................................. 10.5.2 Clear Timing of Status Flags................................................................................ 10.5.3 Interrupt Sources and Activating the DMAC....................................................... 10.6 Notes and Precautions........................................................................................................ 10.6.1 Contention between TCNT Write and Clear........................................................ 10.6.2 Contention between TCNT Word Write and Increment ...................................... 10.6.3 Contention between TCNT Byte Write and Increment........................................ 10.6.4 Contention between GR Write and Compare Match............................................ 10.6.5 Contention between TCNT Write and Overflow/Underflow ............................... 10.6.6 Contention between General Register Read and Input Capture ........................... 10.6.7 Contention Between Counter Clearing by Input Capture and Counter Increment.............................................................................................................. 10.6.8 Contention between General Register Write and Input Capture.......................... 10.6.9 Note on Waveform Cycle Setting ........................................................................ 10.6.10 Contention Between BR Write and Input Capture ............................................... 10.6.11 Note on Writing in the Synchronizing Mode ....................................................... 10.6.12 Note on Setting Reset-synchronized PWM Mode/Complementary PWM Mode .......................................................................................................... 10.6.13 Clearing the Complementary PWM Mode........................................................... 10.6.14 ITU Operating Modes ..........................................................................................
241 241 243 244 244 245 256 258 262 264 272 274 280 281 281 283 284 285 285 286 287 288 289 290 291 292 292 293 294 294 295 295
Section 11 Programmable Timing Pattern Controller (TPC) ............................... 303
11.1 Overview............................................................................................................................ 11.1.1 Features ................................................................................................................ 11.1.2 Block Diagram...................................................................................................... 11.1.3 Input/Output Pins.................................................................................................. 11.1.4 Registers ............................................................................................................... 11.2 Register Descriptions......................................................................................................... 11.2.1 Port B Control Registers 1 and 2 (PBCR1, PCBR2)............................................ 303 303 304 305 306 306 306
11.2.2 Port B Data Register (PBDR)............................................................................... 11.2.3 Next Data Register A (NDRA) ............................................................................ 11.2.4 Next Data Register B (NDRB) ............................................................................. 11.2.5 Next Data Enable Register A (NDERA).............................................................. 11.2.6 Next Data Enable Register B (NDERB) .............................................................. 11.2.7 TPC Output Control Register (TPCR) ................................................................. 11.2.8 TPC Output Mode Register (TPMR) ................................................................... 11.3 Operation ........................................................................................................................... 11.3.1 Overview .............................................................................................................. 11.3.2 Output Timing ...................................................................................................... 11.3.3 Examples of Use of Ordinary TPC Output .......................................................... 11.3.4 TPC Output Non-Overlap Operation.................................................................... 11.3.5 TPC Output by Input Capture .............................................................................. 11.4 Usage Notes ....................................................................................................................... 11.4.1 Non-Overlap Operation........................................................................................
307 308 310 311 312 313 314 316 316 317 317 320 324 325 325
Section 12 Watchdog Timer (WDT) ............................................................................ 327
12.1 Overview............................................................................................................................ 12.1.1 Features ................................................................................................................ 12.1.2 Block Diagram...................................................................................................... 12.1.3 Pin Configuration ................................................................................................. 12.1.4 Register Configuration ......................................................................................... 12.2 Register Descriptions......................................................................................................... 12.2.1 Timer Counter (TCNT) ........................................................................................ 12.2.2 Timer Control/Status Register (TCSR) ................................................................ 12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 12.2.4 Register Access .................................................................................................... 12.3 Operation ........................................................................................................................... 12.3.1 Operation in the Watchdog Timer Mode.............................................................. 12.3.2 Operation in the Interval Timer Mode.................................................................. 12.3.3 Operation in the Standby Mode............................................................................ 12.3.4 Timing of Setting the Overflow Flag (OVF)........................................................ 12.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)........................ 12.4 Usage Notes ....................................................................................................................... 12.4.1 TCNT Write and Count Up Contention ............................................................... 12.4.2 Changing CKS2-CKS0 Bit Values ...................................................................... 12.4.3 Changing Watchdog Timer/Interval Timer Modes .............................................. 12.4.4 System Reset With WDTOVF ............................................................................. 12.4.5 Internal Reset With the Watchdog Timer ............................................................ 327 327 328 328 329 329 329 330 331 333 334 334 336 336 337 337 338 338 338 338 339 339
Section 13 Serial Communication Interface (SCI) .................................................. 341
13.1 Overview............................................................................................................................ 341 13.1.1 Features ................................................................................................................ 341
13.2
13.3
13.4 13.5
13.1.2 Block Diagram...................................................................................................... 13.1.3 Input/Output Pins.................................................................................................. 13.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 13.2.1 Receive Shift Register .......................................................................................... 13.2.2 Receive Data Register .......................................................................................... 13.2.3 Transmit Shift Register ........................................................................................ 13.2.4 Transmit Data Register......................................................................................... 13.2.5 Serial Mode Register ............................................................................................ 13.2.6 Serial Control Register ......................................................................................... 13.2.7 Serial Status Register............................................................................................ 13.2.8 Bit Rate Register (BRR)....................................................................................... Operation ........................................................................................................................... 13.3.1 Overview .............................................................................................................. 13.3.2 Operation in Asynchronous Mode........................................................................ 13.3.3 Multiprocessor Communication ........................................................................... 13.3.4 Clocked Synchronous Operation.......................................................................... SCI Interrupt Sources and the DMAC............................................................................... Usage Notes .......................................................................................................................
342 343 343 344 344 344 344 345 345 347 351 355 363 363 366 376 384 394 394
Section 14 Pin Function Controller (PFC) ................................................................... 399
14.1 Overview............................................................................................................................ 399 14.2 Register Configuration ...................................................................................................... 401 14.3 Register Descriptions......................................................................................................... 401 14.3.1 Port A I/O Register (PAIOR) ............................................................................... 401 14.3.2 Port A Control Registers (PACR1 and PACR2) .................................................. 402 14.3.3 Port B I/O Register (PBIOR)................................................................................ 407 14.3.4 Port B Control Registers (PBCR1 and PBCR2)................................................... 408 14.3.5 Column Address Strobe Pin Control Register (CASCR) ..................................... 413
Section 15 Parallel I/O Ports ............................................................................................ 415
15.1 Overview............................................................................................................................ 415 15.2 Port A................................................................................................................................. 415 15.2.1 Register Configuration ......................................................................................... 415 15.2.2 Port A Data Register (PADR) .............................................................................. 416 15.3 Port B ................................................................................................................................. 417 15.3.1 Register Configuration ......................................................................................... 417 15.3.2 Port B Data Register (PBDR)............................................................................... 418
Section 16 ROM .................................................................................................................. 419
16.1 Overview............................................................................................................................ 419 16.2 PROM Mode...................................................................................................................... 421 16.2.1 Setting the PROM Mode ...................................................................................... 421
16.2.2 Socket Adapter Pin Correspondence and Memory Map ..................................... 16. 3 PROM Programming ......................................................................................................... 16.3.1 Selecting the Programming Mode........................................................................ 16.3.2 Write/Verify and Electrical Characteristics.......................................................... 16.3.3 Points to Note About Writing............................................................................... 16.3.4 Reliability After Writing ......................................................................................
421 423 423 424 428 429
Section 17 RAM .................................................................................................................. 431
17.1 Overview............................................................................................................................ 431 17.2 Operation ........................................................................................................................... 431
Section 18 Power-Down States ...................................................................................... 433
18.1 Overview............................................................................................................................ 18.1.1 Power-Down Modes............................................................................................. 18.1.2 Register................................................................................................................. 18.2 Standby Control Register (SBYCR).................................................................................. 18.3 Sleep Mode........................................................................................................................ 18.3.1 Transition to the Sleep Mode ............................................................................... 18.3.2 Canceling the Sleep Mode.................................................................................... 18.4 S tandby Mode .................................................................................................................... 18.4.1 Transition to the Standby Mode ........................................................................... 18.4.2 Canceling the Standby Mode................................................................................ 18.4.3 Standby Mode Application................................................................................... 433 433 434 434 435 435 435 436 436 438 439
Section 19 Electrical Characteristics ............................................................................ 441
19.1 Absolute Maximum Ratings.............................................................................................. 19.2 DC Characteristics ............................................................................................................. 19.3 AC Characteristics ............................................................................................................. 19.3.1 Clock Timing........................................................................................................ 19.3.2 Control Signal Timing.......................................................................................... 19.3.3 Bus Timing ........................................................................................................... 19.3.4 DMAC Timing ..................................................................................................... 19.3.5 16-bit Integrated Timer Pulse Unit Timing.......................................................... 19.3.6 Programmable Timing Pattern Controller and I/O Port Timing .......................... 19.3.7 Watchdog Timer Timing ...................................................................................... 19.3.8 Serial Communications Interface Timing ............................................................ 19.3.9 AC Characteristics Measurement Conditions ...................................................... 19.4 Usage Note ........................................................................................................................ 441 442 449 449 451 454 490 491 493 494 495 497 498
Appendix A On-Chip Peripheral Module Registers ................................................ 499
A.1 A.2 List of Registers................................................................................................................. 499 Register tables.................................................................................................................... 509 A.2.1 Serial Mode Register (SMR)................................................................................ 509
A.2.2 A.2.3 A.2.4 A.2.5 A.2.6 A.2.7 A.2.8 A.2.9 A.2.10 A.2.11 A.2.12 A.2.13 A.2.14 A.2.15 A.2.16 A.2.17 A.2.18 A.2.19 A.2.20 A.2.21 A.2.22 A.2.23 A.2.24 A.2.25 A.2.26 A.2.27 A.2.28 A.2.29 A.2.30 A.2.31 A.2.32 A.2.33 A.2.34 A.2.35 A.2.36 A.2.37 A.2.38 A.2.39 A.2.40 A.2.41 A.2.42 A.2.43 A.2.44
Bit Rate Register (BRR)....................................................................................... Serial Control Register (SCR).............................................................................. Transmit Data Register (TDR) ............................................................................. Serial Status Register (SSR)................................................................................. Receive Data Register (RDR) .............................................................................. Timer Start Register (TSTR)................................................................................ Timer Synchronization Register (TSNC)............................................................. Timer Mode Register (TMDR) ............................................................................ Timer Function Control Register (TFCR)............................................................ Timer Control Registers 0-4 (TCR0-TCR4) ....................................................... Timer I/O Control Registers 0-4 (TIO0-TIO4)................................................... Timer Interrupt Enable Registers 0-4 (TIER0-TIER4)....................................... Timer Status Registers 0-4 (TSR0-TSR4) .......................................................... Timer Counter 0-4 (TCNT0-TCNT4)................................................................. General Registers A0-4 (GRA0-GRA4) ............................................................. General Registers B0-4 (GRB0-GRB4).............................................................. Buffer Registers A3, A4 (BRA3, BRA4)............................................................. Buffer registers B3, B4 (BRB3, BRB4) ............................................................... Timer Output Control Register (TOCR) .............................................................. DMA Source Address Registers 0-3 (SAR0-SAR3) .......................................... DMA Destination Address Registers 0-3 (DAR0-DAR3).................................. DMA Transfer Count Registers 0-3 (TCR0-TCR3) ........................................... DMA Channel Control Registers 0-3 (CHCR0-CHCR3)................................... DMA Operation Registers (DMAOR) ................................................................. Interrupt Priority Setting Register A (IPRA)........................................................ Interrupt Priority Setting Register B (IPRB)........................................................ Interrupt Priority Setting Register C (IPRC)........................................................ Interrupt Priority Setting Register D (IPRD)........................................................ Interrupt Priority Setting Register E (IPRE) ........................................................ Interrupt Control Register (ICR) .......................................................................... Break Address Register H (BARH) ..................................................................... Break Address Register L (BARL) ...................................................................... Break Address Mask Register H (BAMRH)........................................................ Break Address Mask Register L (BAMRL)......................................................... Break Bus Cycle Register (BBR) ......................................................................... Bus Control Register (BCR) ................................................................................ Wait State Control Register 1 (WCR1)................................................................ Wait State Control Register 2 (WCR2)................................................................ Wait State Control Register 3 (WCR3)................................................................ DRAM Area Control Register (DCR).................................................................. Parity Control Register (PCR).............................................................................. Refresh Control Register (RCR) .......................................................................... Refresh Timer Control/Status Register (RSTCR) ................................................
510 510 512 512 514 515 515 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 535 536 537 538 539 540 541 542 543 544 545 546 548 549 550 552 553 555 556 557
A.2.45 A.2.46 A.2.47 A.2.48 A.2.49 A.2.50 A.2.51 A.2.52 A.2.53 A.2.54 A.2.55 A.2.56 A.2.57 A.2.58 A.2.59 A.2.60 A.2.61 A.2.62 A.2.63 A.2.64
A.3
Refresh Timer Counter Register (RTCNT).......................................................... Refresh Timer Constant Register (RTCOR) ........................................................ Timer Control/Status Register (TCSR) ................................................................ Timer Counter (TCNT) ........................................................................................ Reset Control/Status Register (RSTCSR) ............................................................ Standby Control Register (SBYCR) .................................................................... Port A Data Register (PADR) .............................................................................. Port B Data Register (PBDR)............................................................................... Port A I/O Register (PAIOR) ............................................................................... Port B Data Register (PBIOR) ............................................................................. Port A Control Register 1 (PACR1)..................................................................... Port A Control Register 2 (PACR2)..................................................................... Port B Control Register 1 (PBCR1) ..................................................................... Port B Control Register 2 (PBCR2) ..................................................................... Column Address Strobe Pin Control Register (CASCR) ..................................... TPC Output Mode Register (TPMR) ................................................................... TPC Output Control Register (TPCR) ................................................................. Next Data Enable Register A (NDERA).............................................................. Next Data Enable Register B (NDERB) .............................................................. Next Data Register A (NDRA) (When the output triggers of TPC output groups 0 and 1 are the same) ................................................................................ A.2.65 Next Data Register A (NDRA) (When the output triggers of TPC output groups 0 and 1 are the same) ................................................................................ A.2.66 Next Data Register A (NDRA) (When the output triggers of TPC output groups 0 and 1 are different) ................................................................................ A.2.67 Next Data Register A (NDRA) (When the output triggers of TPC output groups 0 and 1 are different) ................................................................................ A.2.68 Next Data Register B (NDRB) (When the output triggers of TPC output groups 2 and 3 are the same) ................................................................................ A.2.69 Next Data Register B (NDRB) (When the output triggers of TPC output groups 2 and 3 are the same) ................................................................................ A.2.70 Next Data Register B (NDRB) (When the output triggers of TPC output groups 2 and 3 are different) ................................................................................ A.2.71 Next Data Register B (NDRB) (When the output triggers of TPC output groups 2 and 3 are different) ................................................................................ Register Status in Reset and Power-Down States..............................................................
558 559 559 561 561 562 563 564 565 566 567 569 571 573 575 576 577 579 579 580 581 581 582 582 583 584 584 585
Appendix B Pin States ....................................................................................................... 588 Appendix C External Dimensions ................................................................................. 594
Section 1 Overview
1.1 SuperH Microcomputer Features
The SuperH microcomputer (SH7000 series) is a new generation reduced instruction set computer (RISC) in which a Hitachi-original CPU and the peripheral functions required for system configuration are integrated onto a single chip. The CPU has a RISC-type instruction set. Most instructions can be executed in one clock cycle, which strikingly improves instruction execution speed. In addition, the CPU has a 32-bit internal architecture for enhanced data-processing ability. As a result, the CPU enables high-performance systems to be constructed with advanced functionality at low cost, even in applications such as realtime control that require very high speeds, an impossibility with conventional microcomputers. The SH microcomputer includes peripheral functions such as large-capacity ROM, RAM, a direct memory access controller (DMAC), timers, a serial communication interface (SCI), an interrupt controller (INTC), and I/O ports. External memory access support functions enable direct connection to SRAM and DRAM. These features can drastically reduce system cost. For on-chip ROM, masked ROM or electrically programmable ROM (PROM) can be selected. The PROM version can be programmed by users with a general-purpose EPROM programmer. Table 1.1 lists the features of the SH microcomputers (SH7020 and SH7021).
RENESAS 1
Table 1.1
Feature CPU
Features of the SH7020 and SH7021 Microcomputers
Description Original Hitachi architecture 32-bit internal data paths General-register machine: * Sixteen 32-bit general registers * Three 32-bit control registers * Four 32-bit system registers RISC-type instruction set: * Instruction length: 16-bit fixed length for improved code efficiency * Load-store architecture (basic arithmetic and logic operations are executed between registers) * Delayed unconditional branch instructions reduce pipeline disruption * Instruction set optimized for C language Instruction execution time: one instruction/cycle (50 ns/instruction at 20-MHz operation) Address space: 4 Gbytes available on the architecture On-chip multiplier: multiplication operations (16 bits x 16 bits 32 bits) executed in 1-3 cycles, and multiplication/accumulation operations (16 bits x 16 bits + 42 bits 42 bits) executed in 2-3 cycles Five-stage pipeline
Operating modes
Operating modes: * On-chip ROMless mode * On-chip ROM mode Processing states: * Power-on reset state * Manual reset state * Exception processing state * Program execution state * Power-down state * Bus-released state Power-down states: * Sleep mode * Software standby mode
2 RENESAS
Table 1.1
Feature
Features of the SH7020 and SH7021 Microcomputers (cont)
Description Nine external interrupt pins (NMI, IRQ0-IRQ7) Thirty internal interrupt sources Sixteen programmable priority levels
Interrupt controller (INTC)
User break controller (UBC)
Generates an interrupt when the CPU or DMAC generates a bus cycle with specified conditions Simplifies configuration of a self-debugger
Clock pulse generator (CPG)
On-chip clock pulse generator (maximum operating frequency: 20 MHz): * 20-MHz pulses can be generated from a 20-MHz crystal with a duty cycle correcting circuit
Bus state controller (BSC)
Supports external memory access: * Sixteen-bit external data bus Address space divided into eight areas with the following preset features: * Bus size (8 or 16 bits) * Number of wait cycles can be defined by user. * Type of area (external memory area, DRAM area, etc.) -- Simplifies connection to ROM, SRAM, DRAM, and peripheral I/O RAS and CAS signals for DRAM are output Tp cycles can be generated to assure RAS precharge time Address multiplexing is supported internally, so DRAM can be connected directly
* When the DRAM area is accessed: -- -- --
* Chip select signals (CS0 to CS7) are output for each area DRAM refresh function: * Programmable refresh interval * Supports CAS-before-RAS refresh and self-refresh modes DRAM burst access function: * Supports high-speed access modes for DRAM Wait cycles can be inserted by an external WAIT signal One-stage write buffer improves the system performance Data bus parity can be generated and checked
RENESAS 3
Table 1.1 Features of the SH7032 and SH7034 Microcomputers (cont)
Feature Direct memory access controller (DMAC) (4 channels) Description Permits DMA transfer between the following modules: * External memory * External I/O * On-chip memory * Peripheral on-chip modules (except DMAC) DMA transfer can be requested from external pins, on-chip SCI, onchip timers, and on-chip A/D converter Cycle-steal mode or burst mode Channel priority level is selectable Channels 0 and 1: dual or single address transfer mode is selectable; external request sources are supported; Channels 2 and 3: dual address transfer mode, internal request sources only 16-bit integrated-timer pulse unit (ITU) Ten types of waveforms can be output Input pulse width and cycle can be measured PWM mode: pulse output with 0-100% duty cycle (maximum resolution: 50 ns) Complementary PWM mode: can output a maximum of three pairs of non-overlapping PWM waveforms Phase counting mode: can count up or down according to the phase of an external two-phase clock Timing pattern controller (TPC) Maximum 16-bit output (4 bits x 4 channels) can be output Non-overlap intervals can be established between pairs of waveforms Timing-source timer is selectable Watchdog timer (WDT) (1 channel) Can be used as watchdog timer or interval timer Timer overflow can generate an internal reset, external signal, or interrupt Power-on reset or manual reset can be selected as the internal reset Serial communication Asynchronous or clocked synchronous mode is selectable interface (SCI) (2 channels) Can transmit and receive simultaneously (full duplex) On-chip baud rate generator in each channel Multiprocessor communication function
4 RENESAS
Table 1.1
Feature I/O ports
Features of the SH7032 and SH7034 Microcomputers (cont)
Description Total of 40 I/O lines (32 input/output lines, 8 input-only lines): * Port A: 16 input/output lines (input or output can be selected for each bit) * Port B: 16 input/output lines (input or output can be selected for each bit)
On-chip memory
SH7020: 16-kbyte masked ROM, and 1-kbyte RAM SH7021: 32-kbyte electrically programmable ROM or masked Rom, and 1-kbyte RAM 32-bit data can be accessed in one clock cycle
RENESAS 5
Table 1.2
Operating Frequency Model HD6437021X HD6437021XI HD6437021VX HD6437021VXI HD6477021X HD6477021XI HD6477021VX HD6477021VXI HD6437020X HD6437020XI HD6437020VX HD6437020VXI HD6417020SX20I HD6417020SVX12I HD6437021VTE HD6437021VTEI HD6477021TE HD6477021TEI HD6477021VTE HD6477021VTEI HD6437020TE HD6437020TEI HD6437020VTE HD6437020VTEI HD6417020X20I HD6417020VX12I HD6437021TEI HD6437021TE 2 to 20MHz 2 to 16.6MHz 2 to 12.5MHz -40 to +85 C 2 to 20MHz 2 to 16.6MHz 2 to 12.5MHz -40 to +85 C 2 to 20MHz 2 to 16.6MHz 2 to 12.5MHz -40 to +85 C 2 to 20MHz 2 to 12.5MHz -40 to +85 C -40 to +85 C -20 to +75 C -40 to +85 C -20 to +75 C -20 to +75 C -40 to +85 C -20 to +75 C -20 to +75 C -40 to +85 C -20 to +75 C Operating temperature Marking Model No. Package 100-pin
Product Line
Product Number
On-Chip ROM
Operating Voltage
SH7021
masked
5.0V
ROM
plastic TQFP (TFP-100B)
3.3V
PROM
5.0V
3.3V
SH7020
masked
5.0V
ROM
3.3V
ROMless
5.0V
3.3V
6 RENESAS
1.2
Block Diagram
PA15/IRQ3/DREQ1 PA14/IRQ2/DACK1 PA13/IRQ1/DREQ0/TCLKB PA12/IRQ0/DACK0/TCLKA PA11/DPH/TIOCB1 PA10/DPL/TIOCA1 PA9/AH/IRQOUT/ADTRG PA8/BREQ PA7/BACK PA6/RD PA5/WRH (LBS) PA4/WRL (WR) PA3/CS7/WAIT PA2/CS6/TIOCB0 PA1/CS5/RAS PA0/CS4/TIOCA0
Port A
CS3/CASL CS2 CS1/CASH CS0 A21 A20 A19 A18 A17 A16
Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (HBS) AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 RAM*1
RES(Vpp)*2 WDTOVF MD2 MD1 MD0 NMI
PROM or masked ROM*1
CK EXTAL XTAL VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AVref AVCC AVSS
;;;; ;;;; ;;;; ;;;; ;;;; ;;;; ;;;; ;;;; ;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;; ;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Direct ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;; memory CPU ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;; access ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;; controller ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
User Interrupt break controller controller
Clock pulse generator
Bus state controller
Serial communication interface (2 channels) Programmable timing pattern controller
16-bit integrated-timer pulse unit
Watchdog timer
Port B
: Peripheral address bus (24 bits)
;;;;; : Internal upper data bus (16 bits) ;;;;; ;;;;; : Internal lower data bus (16 bits) ;;;;;
: Peripheral data bus (16 bits) : Internal address bus (24 bits)
Notes: *1. SH7020: 16-kbyte masked ROM and 1-kbyte RAM. SH7021: 32-kbyte PROM or Masked ROM and 1-kbyte RAM. *2. Vpp: SH7021 (PROM version)
Figure 1.1 Block Diagram
RENESAS 7
PB15/TP15/IRQ7 PB14/TP14/IRQ6 PB13/TP13/IRQ5/SCK1 PB12/TP12/IRQ4/SCK0 PB11/TP11/TxD1 PB10/TP10/RxD1 PB9/TP9/TxD0 PB8/TP8/RxD0 PB7/TP7/TOCXB4/TCLKD PB6/TP6/TOCXA4/TCLKC PB5/TP5/TIOCB4 PB4/TP4/TIOCA4 PB3/TP3/TIOCB3 PB2/TP2/TIOCA3 PB1/TP1/TIOCB2 PB0/TP0/TIOCA2
Data/address
Address
1.3
1.3.1
Pin Descriptions
Pin Arrangement
AD0 AD1 AD2 VSS AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 VCC AD11 VSS AD12 AD13 AD14 AD15 A0(HBS) A1 A2 A3 VSS A4
Notes: Vpp: SH7021 (PROM version)
8 RENESAS
A5 A6 A7 A8 A9 A10 VSS A11 A12 A13 A14 A15 VCC A16 A17 VSS A18 A19 A20 A21 CS0 CS1/CASH CS2 CS3/CASL VSS
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PB15/TP15/IRQ7 PB14/TP14/IRQ6 PB13/TP13/IRQ5/SCK1 PB12/TP12/IRQ4/SCK0 PB11/TP11/TxD1 PB10/TP10/RxD1 PB9/TP9/TxD0 PB8/TP8/RxD0 VSS PB7/TP7/TOCXB4/TCLKD PB6/TP6/TOCXA4/TCLKC PB5/TP5/TIOCB4 VCC PB4/TP4/TIOCA4 PB3/TP3/TIOCB3 PB2/TP2/TIOCA3 PB1/TP1/TIOCB2 PB0/TP0/TIOCA2 VSS VSS VCC MD2 MD1 MD0 RES(Vpp)*
TFP-100B (Top view)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
WDTOVF NMI VCC XTAL EXTAL VSS CK PA15/IRQ3/DREQ1 PA14/IRQ2/DACK1 PA13/IRQ1/DREQ0/TCLKB PA12/IRQ0/DACK0/TCLKA PA11/DPH/TICOB1 VCC PA10/DPL/TIOCA1 PA9/AH/IRQOUT PA8/BREQ VSS PA7/BACK PA6/RD PA5/WRH(LBS) PA4/WRL(WR) PA3/CA7/WAIT PA2/CS6/TIOCB0 PA1/CS5/RAS PA0/CS4/TIOCA0
Figure 1.2 Pin Arrangement
1.3.2
Pin Functions
Table 1.3 describes the pin functions. Table 1.3
Type Power
Pin Functions
Symbol VCC Pin No. 13, 38, 63, 73, 80, 88 4, 15, 24, 32, 41, 50, 59, 70, 81, 82, 92 76* I/O I Name and Function Power: Connected to the power supply. Connect all VCC pins to the system power supply . The chip will not operate if any VCC pin is left unconnected. Ground: Connected to ground. Connect all V SS pins to the system ground. The chip will not operate if any VSS pin is left unconnected.
VSS
I
VPP
I
RES pin in the MCU mode. Apply +12.5V when programming the PROM in the SH7021 (PROM version). Crystal/external clock: Connected to a crystal resonator or external clock input having the same frequency as the system clock (CK). Crystal: Connected to a crystal resonator with the same frequency as the system clock (CK). If an external clock is input at the EXTAL pin, leave XTAL open. System clock: Supplies the system clock (CK) to peripheral devices. Reset: Low input causes a power-on reset if NMI is high, or a manual reset if NMI is low. Watchdog timer overflow: Overflow output signal from the watchdog timer. Bus request: Driven low by an external device to request the bus ownership. Bus request acknowledge: Indicates that bus ownership has been granted to an external device. By receiving the BACK signal, a device that has sent a BREQ signal can confirm that it has been granted the bus.
Clock
EXTAL
71
I
XTAL
72
I
CK System control RES WDTOVF BREQ BACK
69 76 75 60 58
O I O I O
Note: Pin 76 is RES in the SH7020, SH7021 (Masked ROM version) and Vpp in the SH7021 (PROM version).
RENESAS 9
Table 1.3
Type
Pin Functions (cont)
Symbol Pin No. 79-77 I/O I Name and Function Mode select: Selects the operating mode. Do not change these inputs while the chip is operating. The following table lists the possible operating modes and their corresponding MD2-MD0 values. Operating MD2 MD1 MD0 Mode 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 PROM mode* 2 (Reserved) Enabled*
1
Operating MD2, mode MD1, control MD0
On-chip ROM Disabled
Bus Size in Area 0 8 bits 16 bits
MCU mode
Interrupts
NMI
74
I
Nonmaskable interrupt: Nonmaskable interrupt request signal. The rising or falling edge can be selected for signal detection. Interrupt request 0-7: Maskable interrupt request signals. Level input or edge-triggered input can be selected. Slave interrupt request output: Indicates occurrence of an interrupt while the bus is released. Address bus: Outputs addresses.
IRQ0- IRQ7 IRQOUT Address bus A21-A0
65-68, 97-100 61
I
O
45-42, 40, O 39, 37-33, 31-25, 23-20 19-16, 14, I/O 12-5, 3-1 64 62 54 I/O I/O I
Data bus
AD15- AD0 DPH DPL
Data bus: 16-bit bidirectional data bus that is multiplexed with the lower 16 bits of the address bus. Upper data bus parity: Parity data for D15-D8. Lower data bus parity: Parity data for D7-D0. Wait: Requests the insertion of wait states (T W ) into the bus cycle when the external address space is accessed.
Bus control
WAIT
Notes : 1.Use prohibited in the SH7020 Romless version. 2.Can only be used in the SH7021 ZTAT version.
10 RENESAS
Table 1.3
Type Bus control (cont)
Pin Functions (cont)
Symbol RAS CASH Pin No. 52 47 I/O O O Name and Function Row address strobe: DRAM row-address strobe-timing signal. Column address strobe high: DRAM column-address strobe-timing signal outputs low level to access the upper eight data bits. Column address strobe low: DRAM column-address strobe-timing signal outputs low level to access the lower eight data bits. Read: Indicates reading of data from an external device. Upper write: Indicates write access to the upper eight bits of an external device. Lower write: Indicates write access to the lower eight bits of an external device. Chip select 0-7: Chip select signals for accessing external memory and devices. Address hold: Address hold timing signal for a device using a multiplexed address/data bus. Upper/lower byte strobe: Upper and lower byte strobe signals. (Also used as WRH and A0.) Write: Brought low during write access. (Also used as WRL.) DMA transfer request (channels 0 and 1): Input pins for external DMA transfer requests. DMA transfer acknowledge (channels 0 and 1): Indicates that DMA transfer is acknowledged. ITU input capture/output compare (channel 0): Input capture or output compare pins. ITU input capture/output compare (channel 1): Input capture or output compare pins. ITU input capture/output compare (channel 2): Input capture or output compare pins. ITU input capture/output compare (channel 3): Input capture or output compare pins. ITU input capture/output compare (channel 4): Input capture or output compare pins.
CASL
49
O
RD WRH WRL CS0-CS7 AH
57 56 55 46-49, 51-54 61
O O O O O O O I O I/O I/O I/O I/O I/O
HBS, LBS 20, 56 WR DMAC DREQ0, DREQ1 DACK0, DACK1 16-bit integratedtimer pulse unit (ITU) TIOCA0, TIOCB0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3 TIOCA4, TIOCB4 55 66, 68 65, 67 51, 53 62, 64 83, 84 85, 86 87, 89
RENESAS 11
Table 1.3
Type 16-bit integratedtimer pulse unit (ITU) Timing pattern controller (TPC) Serial communication interface (SCI)
Pin Functions (cont)
Symbol TOCXA4, TOCXB4 TCLKA- TCLKD TP15- TP0 Pin No. 90, 91 65, 66, 90, 91 100-93, 91-89, 87-83 94, 96 I/O O I O Name and Function ITU output compare (channel 4): Output compare pins. ITU timer clock input: External clock input pins for ITU counters. Timing pattern output 15-0: Timing pattern output pins.
TxD0, TxD1 RxD0, RxD1 SCK0, SCK1
O
Transmit data (channels 0 and 1): Transmit data output pins for SCI0 and SCI1. Receive data (channels 0 and 1): Receive data input pins for SCI0 and SCI1. Serial clock (channels 0 and 1): Clock input/output pins for SCI0 and SCI1. Port A: 16-bit input/output pins. Input or output can be selected individually for each bit. Port B: 16-bit input/output pins. Input or output can be selected individually for each bit.
93, 95 97, 98 68-64, 62-60, 58-51 100-93, 91-89, 87-83
I I/O I/O
I/O ports
PA15- PA0 PB15- PB0
I/O
12 RENESAS
1.3.3
Pin Layout by Mode
Table 1.4 shows pin layout by mode Table 1.4 Pin Layout by Mode
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PROM Mode (SH7021PROM version) AD0 AD1 AD2 Vss AD3 AD4 AD5 AD6 AD7 NC NC NC VCC NC VSS NC NC NC NC A0 A1 A2 A3 VSS A4 A5 A6 A7 Pin No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 PROM Mode (SH7021PROM version) A8 OE A10 VSS A11 A12 A13 A14 A15 VCC A16 VCC VSS VCC NC NC NC NC NC NC NC VSS NC NC PGM CE NC NC
MCU Mode AD0 AD1 AD2 Vss AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 VCC AD11 VSS AD12 AD13 AD14 AD15 A0(HBS) A1 A2 A3 VSS A4 A5 A6 A7
MCU Mode A8 A9 A10 VSS A11 A12 A13 A14 A15 VCC A16 A17 VSS A18 A19 A20 A21 CS0 CS1/CASH CS2 CS3/CASL VSS PA0/CS4/TIOCA0 PA1/CS5/RAS PA2/CS6/ TIOCB0 PA3/CS7/WAIT PA4/WRL(WR) PA5/WRH(LBS)
RENESAS 13
Table 1.3.3 Pin Layout by Mode (cont)
Pin No. 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 PROM Mode (SH7021PROM version) NC NC VSS NC NC NC VCC NC NC NC NC NC NC VSS NC NC VCC A9 NC Vpp VCC VCC VCC 99 100 98 92 93 94 95 96 97 Pin No. 80 81 82 83 84 85 86 87 88 89 90 91 PROM Mode (SH7021PROM version) VCC VSS VSS NC NC NC NC NC VCC NC NC NC VSS NC NC NC NC NC NC NC NC
MCU Mode PA6/RD PA7/BACK VSS PA8/BREQ PA9/AH/IRQOUT PA10/DPL/TIOCA1 VCC PA11/DPH/TIOCB1 PA12/IRQ0/DACK0/ TCLKA PA13/IRQ1/DREQ0/ TCLKLB PA14/IRQ2/DACK1 PA15/IRQ3/DREQ1 CK VSS EXTAL XTAL VCC NMI WDTOVF RES MD0 MD1 MD2
MCU Mode VCC VSS VSS PB0/TP0/TIOCA2 PB1/TP1/TIOCB2 PB2/TP2/TIOCA3 PB3/TP3/TIOCB3 PB4/TP4/TIOCA4 VCC PB5/TP5/TIOCB4 PB6/TP6/TOCXA4/ TCLKC PB7/TP7/TOCXB4/ TCLKD VSS PB8/TP8/RxD0 PB9/TP9/TxD0 PB10/TP10/RxD1 PB11/TP11/TXD1 PB12/TP12/IRQ4/ SCK0 PB13/TP13/IRQ5/ SCK1 PB14/TP14/IRQ6 PB15/TP15/IRQ7
14 RENESAS
Section 2 CPU
2.1 Register Configuration
The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four 32-bit system registers. 2.1.1 General Registers (Rn)
General registers Rn consist of sixteen 32-bit registers (R0-R15). General registers are used for data processing and address calculation. Register R0 also functions as an index register. For some instructions, the R0 register must be used. Register R15 functions as a stack pointer to save or recover status registers (SR) and program counter (PC) during exception processing.
31 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP
0 R0 functions as an index register in the indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a source register or a destination register.
R15 functions as a stack pointer (SP) during exception processing.
Figure 2.1 General Registers (Rn) 2.1.2 Control Registers
Control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register
RENESAS15
functions as a base address for the indirect GBR addressing mode to transfer data to the registers of peripheral on-chip modules. The vector base register functions as the base address of the exception processing vector area including interrupts.
31 SR
9 8 7 6 5 4 32 1 0 M Q I3 I2 I1 I0 ST SR: Status register T bit: The MOVT, CMP, TAS, TST, BT, BF, SETT, and CLRT instructions use the T bit to indicate a true (1) or false (0). The ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S, DIV1, NEGC, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR and ROTCL instructions also use the T bit to indicate carry/borrow or overflow/underflow S bit: Used by the MAC instruction. Reserved bits. These bits always read 0. The write value should always be 0. Bits I0-I3: Interrupt mask bits. M and Q bits: Used by the DIV0U, DIV0S, and DIV1 instructions.
31 GBR
Global base register (GBR): 0 Indicates the base address of the indirect GBR addressing mode. The indirect GBR addressing mode is used to transfer data to the register areas peripheral on-chip modules. 0 Vector base register (VBR): Stores the base address of the exception processing vector area.
31 VBR
Figure 2.2 Control Registers 2.1.3 System Registers
System registers consist of four 32-bit registers: multiply and accumulate registers high and low (MACH and MACL), procedure register (PR), and program counter (PC). The multiply and accumulate registers store the results of multiply and accumulate operations. The procedure register stores the return address from the subroutine procedure. The program counter stores program addresses to control the flow of the processing.
16 RENESAS
31 (sign extended) MACL
9 MACH
0
Multiply and accumulate (MAC) registers high and low (MACH, MACL): Store the results of multiply and accumulate operations. MACH is sign-extended when read because only the lowest 10 bits are valid. Procedure register (PR): Stores a return address from a subroutine procedure. Program counter (PC): Indicates the fourth byte (second instruction) after the current instruction.
31 PR
0
31 PC
0
Figure 2.3 System Registers 2.1.4 Initial Values of Registers
Table 2.1 lists the values of the registers after reset. Table 2.1 Initial Values of Registers
Register R0-R14 R15 (SP) Control register SR GBR VBR System register MACH, MACL, PR PC Initial Value Undefined Value of the stack pointer in the vector address table Bits I0-I3 are 1111(H'F), reserved bits are 0, and other bits are undefined Undefined H'00000000 Undefined Value of the program counter in the vector address table
Classification General register
2.2
2.2.1
Data Formats
Data Format in Registers
Register operands are always long words (32 bits). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a long word when stored into a register (figure 2.4).
RENESAS17
31 Long word
0
Figure 2.4 Data Format in Registers 2.2.2 Data Format in Memory
Memory data formats are classified into bytes, words, and long words. Byte data can be accessed from any address, but an address error will occur if you try to access word data starting from an address other than 2n or long word data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, which is referred to by the hardware stack pointer (SP, R15), uses only long word data starting from address 4n because this area stores the program counter and status register (figure 2.5).
Address m + 1 Address m 23 31
Address m + 3
Address m + 2 7 15
0
7 Byte 0 7 Byte 0 7 Byte 0 7 Byte 0 Address 2n Address 4n 15 31 Word 0 15 Long word Word 0 0
Figure 2.5 Data Format in Memory 2.2.3 Immediate Data Format
Byte (8-bit) immediate data is located in the instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and is handled in registers as long word data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and is handled as long word data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. Word or long word immediate data is not located in the instruction code but rather is stored in a memory table. The memory table is accessed by a immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement.
18 RENESAS
2.3
2.3.1
Instruction Features
RISC-Type Instruction Set
All instructions are RISC type. Their features are as follows: 16-Bit Fixed Length: Every instruction is 16 bits long, making program coding much more efficient. One Instruction/Cycle: Basic instructions can be executed in one cycle using the pipeline system. One-cycle instructions are executed in 50 ns at 20 MHz. Data Length: Long word is the standard data length for all operations. Memory can be accessed in bytes, words, or long words. Byte or word data accessed from memory is sign-extended and handled as long word data. Immediate data is sign-extended for arithmetic operations or zeroextended for logic operations (handled as long word data). Table 2.2 Sign Extension of Word Data
Description Data is sign-extended to 32 bits, and R1 becomes H'00001234. It is next operated upon by an ADD instruction. Conventional CPUs ADD.W #H'1234, R0
CPU of SH7000 Series MOV.W @(disp,PC),R1 ADD R1,R0 ...................... .. .DATA.W H'1234
Note: The address of the immediate data is accessed by @(disp, PC).
Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Delayed Branch Instructions: Unconditional branch instructions are delayed. Pipeline disruption during branching is reduced by first executing the instruction that follows the branch instruction, and then branching. See the SH-1/SH-2 Programming Manual for details. Table 2.3 Delayed Branch Instructions
Description Executes an ADD before branching to TRGET. Conventional CPU ADD.W BRA R1, R0 TRGET
CPU of SH7000 Series BRA ADD TRGET R1, R0
Multiplication/Accumulation Operation: The five-stage pipeline system and the on-chip multiplier enable 16-bit x 16-bit 32-bit multiplication operations to be executed in 1-3 cycles. 16-bit x 16-bit + 42-bit 42-bit multiplication/accumulation operations can be executed in 2-3
RENESAS19
cycles. T bit: T bit (in the status register) is set according to the result of a comparison, and in turn is the condition (True/False) that determines if the program will branch. The T bit in the status register is only changed by selected instructions, thus improving the processing speed. Table 2.4 T bit
Description T bit is set when R0 R1. The program branches to TRGET0 when R0 R1 and to TRGET1 when R0CPU of SH7000 Series CMP/GE R1, R0 BT TRGET0 BF TRGET1 ADD TST BT #-1, R0 R0, R0 TRGET
Immediate Data: Byte (8-bit) immediate data is located in the instruction code. Word or long word immediate data is not located in instruction codes but is stored in a memory table. The memory table is accessed by a immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. Table 2.5 Immediate Data Accessing
CPU of SH7000 Series MOV #H'12, R0 Conventional CPU MOV.B MOV.W #H'12, R0 #H'1234, R0
Classification 8-bit immediate 16-bit immediate
MOV.W @(disp,PC), R0 ......... .DATA.W H'1234 MOV.L @(disp,PC), R0 ......... .DATA.L H'12345678
32-bit immediate
MOV.L
#H'12345678, R0
Note: The address of the immediate data is accessed by @(disp, PC).
Absolute Address: When data is accessed by absolute address, the value already in the absolute address is placed in the memory table. By loading the immediate data when the instruction is executed, that value is transferred to the register and the data is accessed in the indirect register addressing mode.
20 RENESAS
Table 2.6
Absolute Address Accessing
CPU of SH7000 Series MOV.L @(disp,PC), R1 MOV. B @R1, R0 ......... .DATA.L H'12345678 Conventional CPU MOV.B @H'12345678, R0
Classification Absolute address
Note: The address of the immediate data is accessed by @(disp, PC).
16/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the pre-existing displacement value is placed in the memory table. By loading the immediate data when the instruction is executed, that value is transferred to the register and the data is accessed in the indirect indexed register addressing mode. Table 2.7 Accessing by Displacement
CPU of SH7000 Series MOV.W @(disp, PC), R0 MOV.W @(R0, R1), R2 ......... .DATA.W H'1234 Conventional CPU MOV.W @(H'1234, R1), R2
Classification 16-bit displacement
Note: The address of the immediate data is accessed by @(disp, PC).
RENESAS21
2.3.2
Addressing Modes
Addressing modes and effective address calculation are described in table 2.8. Table 2.8 Addressing Modes and Effective Addresses
Effective Addresses Calculation The effective address is register Rn. (The operand is the contents of register Rn.) The effective address is the content of register Rn. Rn @Rn + Rn Rn (After the instruction is executed) Byte: Rn + 1 Rn Word: Rn + 2 Rn Long word: Rn + 4 Rn Byte: Rn - 1 Rn Word: Rn - 2 Rn Long word: Rn - 4 Rn (Instruction executed with Rn after calculation) Equation --
Addressing Mnemonic Mode Expression Direct register addressing Indirect register addressing Post-increment indirect register addressing Rn
@Rn
Rn
The effective address is the content of register Rn. A constant is added to the content of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a long word operation. Rn Rn + 1/2/4 1/2/4 + Rn
Pre-decrement indirect register addressing
@-Rn
The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a long word operation. Rn Rn - 1/2/4 1/2/4 - Rn - 1/2/4
22 RENESAS
Table 2.8
Addressing Modes and Effective Addresses (cont)
Effective Addresses Calculation The effective address is Rn plus a 4-bit displacement (disp). disp is zero-extended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a long word operation. Rn disp (zero-extended) x 1/2/4 + Rn + disp x 1/2/4 Equation Byte: Rn + disp Word: Rn + disp x 2 Long word: Rn + disp x 4
Addressing Mnemonic Mode Expression Indirect register addressing with displacement @(disp:4, Rn)
Indirect indexed register addressing
@(R0, Rn)
The effective address is the Rn value plus R0. Rn + R0 Rn + R0
Rn + R0
Indirect GBR addressing with displacement
@(disp:8, GBR)
The effective address is the GBR value plus an 8-bit displacement (disp). The value of disp is zeroextended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a long word operation. GBR disp (zero-extended) x 1/2/4 + GBR + disp x 1/2/4
Byte: GBR + disp Word: GBR + disp x 2 Long word: GBR + disp x 4
Indirect indexed GBR addressing
@(R0, GBR)
The effective address is the GBR value plus the R0. GBR + R0 GBR + R0
GBR + R0
RENESAS23
Table 2.8
Addressing Modes and Effective Addresses (cont)
Effective Addresses Calculation The effective address is the PC value plus an 8-bit displacement (disp). disp is zero-extended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a long word operation. For a long word operation, the lowest two bits of the PC are masked. PC &* H'FFFFFFFC disp (zero-extended) x 2/4 *: For long word + PC + disp x 2 or PC & H'FFFFFFFC + disp x 4 Equation Word: PC + disp x 2 Long word: PC & H'FFFFFFFC + disp x 4
Addressing Mnemonic Mode Expression PC relative addressing with displacement @(disp:8, PC)
PC relative addressing
disp:8
The effective address is the PC value sign-extended with an 8-bit displacement (disp), doubled, and added to the PC. PC disp (zero-extended) x 2 + PC + disp x 2
PC + disp x 2
disp:12
The effective address is the PC value sign-extended with a 12-bit displacement (disp), doubled, and added to the PC. PC disp (zero-extended) x 2 + PC + disp x 2
PC + disp x 2
24 RENESAS
Table 2.8
Addressing Modes and Effective Addresses (cont)
Effective Addresses Calculation The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions are zero-extended. The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions are sign-extended. Immediate data (imm) for the TRAPA instruction is zero-extended and is quadrupled. Equation -- -- --
Addressing Mnemonic Mode Expression Immediate addressing #imm:8 #imm:8 #imm:8
2.3.3
Instruction Formats
The instruction format refers to the source operand and the destination operand. The meaning of the operand depends on the instruction code. Symbols are as follows. Instruction code mmmm Source register nnnn Destination register iiii Immediate data dddd Displacement
xxxx
Table 2.9
Instruction Formats
Source Operand -- 0 xxxx xxxx xxxx -- nnnn: Direct register nnnn: Direct register nnnn: Indirect predecrement register MOVT Rn Destination Operand -- Instruction Example NOP
Instruction Formats 0 format 15 xxxx n format
15 xxxx nnnn xxxx xxxx
0
Control register or system register Control register or system register
STS
MACH,Rn
STC.L
SR,@-Rn
RENESAS25
Table 2.9
Instruction Formats (cont)
Source Operand mmmm: Direct register 0 mmmm: Indirect post-increment register mmmm: Direct register Destination Operand Control register or system register Control register or system register -- nnnn: Direct register nnnn: Direct register Instruction Example LDC Rm,SR
Instruction Formats m format 15 xxxx mmmm xxxx xxxx
LDC.L @Rm+,SR JMP ADD MOV.L @Rm Rm,Rn Rm,@Rn
nm format 15 xxxx nnnn mmmm xxxx 0
mmmm: Direct register mmmm: Direct register
mmmm: Indirect MACH, MACL post-increment register (multiply/ accumulate) nnnn: Indirect post-increment register (multiply/ accumulate)* mmmm: Indirect post-increment register mmmm: Direct register mmmm: Direct register md format 15 xxxx nd4 format 15 xxxx xxxx nnnn dddd 0 xxxx mmmm dddd 0 mmmmdddd: indirect register with displacement R0 (Direct register) nnnn: Direct register nnnn: Indirect predecrement register nnnn: Indirect indexed register
MAC.W @Rm+,@Rn+
MOV.L @Rm+,Rn MOV.L Rn Rm,@-
MOV.L Rm,@(R0,Rn)
R0 (Direct register) MOV.B @(disp,Rm),R0
nnnndddd: Indirect register with displacement
MOV.B R0,@(disp,Rn)
Note: In MAC instructions, nnnn is the source register.
26 RENESAS
Table 2.9
Instruction Formats (cont)
Source Operand mmmm: Direct register Destination Operand nnnndddd: Indirect register with displacement nnnn: Direct register Example MOV.L Rm,@(disp,Rn)
Instruction Formats nmd format 15 xxxx nnnn mmmm dddd 0
mmmmdddd: Indirect register with displacement d format 15 xxxx xxxx dddd dddd 0 dddddddd: Indirect GBR with displacement R0(Direct register) dddddddd: PC relative with displacement dddddddd: PC relative d12 format 15 xxxx nd8 format 15 xxxx i format 15 xxxx xxxx iiii iiii iiiiiiii: Immediate ni format 15 xxxx nnnn iiii iiii 0 iiiiiiii: Immediate 0 nnnn dddd dddd 0 dddd dddd dddd dddddddd: PC relative with displacement iiiiiiii: Immediate iiiiiiii: Immediate 0 dddddddddddd: PC relative
MOV.L @(disp,Rm),Rn
R0 (Direct register) MOV.L @(disp,GBR),R0
dddddddd: Indirect GBR with displacement
MOV.L R0,@(disp,GBR)
R0 (Direct register) MOVA @(disp,PC),R0 -- -- BF BRA disp disp
nnnn: Direct register
MOV.L @(disp,PC),Rn
Indirect indexed GBR
AND.B #imm,@(R0,GBR) #imm,R0
R0 (Direct register) AND
-- nnnn: Direct register
TRAPA ADD
#imm #imm,Rn
RENESAS27
2.4
2.4.1
Instruction Set
Instruction Set by Classification
Table 2.10 lists instructions by classification. Table 2.10 Classification of Instructions
Classification Data transfer Types 5 Operation Code MOV Function Data transfer, immediate data transfer, peripheral module data transfer, structure data transfer Effective address transfer T bit transfer Swap of upper and lower bytes Extraction of the middle of registers connected Binary addition Binary addition with carry Binary addition with overflow check Comparison Division Initialization of signed division Initialization of unsigned division Sign extension Zero extension Multiplication and accumulation Signed multiplication Unsigned multiplication Negation Negation with borrow Binary subtraction Binary subtraction with carry Binary subtraction with underflow check Logical AND Bit inversion Logical OR Memory test and bit set 14 28 Number of Instructions 39
MOVA MOVT SWAP XTRCT Arithmetic operations 17 ADD ADDC ADDV CMP/cond DIV1 DIV0S DIV0U EXTS EXTU MAC MULS MULU NEG NEGC SUB SUBC SUBV Logic operations 6 AND NOT OR TAS
28 RENESAS
Table 2.10 Classification of Instructions (cont)
Classification Logic operations(cont) Shift Types 6 10 Operation Code TST XOR ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch 7 BF BT BRA BSR JMP JSR RTS System control 11 CLRT CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Total 56 Function Logical AND and T bit set Exclusive OR One-bit left rotation One-bit right rotation One-bit left rotation with T bit One-bit right rotation with T bit One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift Conditional branch (T = 0) Conditional branch (T = 1) Unconditional branch Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure T bit clear MAC register clear Load to control register Load to system register No operation Return from exception processing T bit set Shift into power-down mode Storing control register data Storing system register data Trap exception processing 133 31 7 14 Number of Instructions 14
RENESAS29
Instruction codes, operation, and execution states are listed in the following format in order by classification. Table 2.11 Instruction Code Format
Item Instruction mnemonic Format OP.Sz Explanation SRC,DEST OP: Operation code Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement* mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 ........... 1111: R15 iiii: Immediate data dddd: Displacement Direction of transfer Memory operand Flag bits in the SR Logical AND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n-bit shift Value when no wait states are inserted Instruction execution cycles: The execution cycles shown in the table are minimums. The actual number of cycles may be increased: 1. When contention occurs between instruction fetches and data access, or 2. When the destination register of the load instruction (memory register) and the register used by the next instruction are the same. T bit -- Value of T bit after instruction is executed No change
Instruction code
MSB LSB
Operation summary
, (xx) M/Q/T & | ^ ~ <>n
Execution cycle
Note: Scaling (x1, x2, x4) is performed according to the instruction operand size. See "SH-1/SH-2 Programming Manual" for details.
30 RENESAS
Table 2.12 Data Transfer Instructions
Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Instruction MOV MOV.W MOV.L MOV MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W #imm,Rn
Instruction Code 1110nnnniiiiiiii
Operation #imm Sign extension Rn (dispx2 + PC) Sign extension Rn (dispx4 + PC) Rn Rm Rn Rm (Rn) Rm (Rn) Rm (Rn) (Rm) Sign extension Rn (Rm) Sign extension Rn (Rm) Rn Rn-1 Rn, Rm (Rn) Rn-2 Rn, Rm (Rn) Rn-4 Rn, Rm (Rn) (Rm) Sign extension Rn,Rm + 1 Rm (Rm) Sign extension Rn,Rm + 2 Rm (Rm) Rn,Rm + 4 Rm R0 (disp + Rn) R0 (dispx2 + Rn) Rm (dispx4 + Rn) (disp + Rm) Sign extension R0 (dispx2 + Rm) Sign extension R0 (dispx4 + Rm) Rn Rm (R0 + Rn) Rm (R0 + Rn)
@(disp,PC),Rn 1001nnnndddddddd @(disp,PC),Rn 1101nnnndddddddd Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn @Rm,Rn @Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn @Rm+,Rn @Rm+,Rn 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 0110nnnnmmmm0110
R0,@(disp,Rn) 10000000nnnndddd R0,@(disp,Rn) 10000001nnnndddd Rm,@(disp,Rn) 0001nnnnmmmmdddd @(disp,Rm),R0 10000100mmmmdddd @(disp,Rm),R0 10000101mmmmdddd @(disp,Rm),Rn 0101nnnnmmmmdddd Rm,@(R0,Rn) Rm,@(R0,Rn) 0000nnnnmmmm0100 0000nnnnmmmm0101
RENESAS31
Table 2.12 Data Transfer Instructions (cont)
Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Instruction MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn R0,@(disp,GBR) R0,@(disp,GBR) R0,@(disp,GBR) @(disp,GBR),R0 @(disp,GBR),R0 @(disp,GBR),R0 @(disp,PC),R0 Rn
Instruction Code 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd 11000101dddddddd 11000110dddddddd 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 0010nnnnmmmm1101
Operation Rm (R0 + Rn) (R0 + Rm) Sign extension Rn (R0 + Rm) Sign extension Rn (R0 + Rm) Rn R0 (disp + GBR) R0 (dispx2 + GBR) R0 (dispx4 + GBR) (disp + GBR) Sign extension R0 (dispx2 + GBR) Sign extension R0 (dispx4 + GBR) R0 dispx4 + PC R0 T Rn Rm Swap the bottom two bytes Rn Rm Swap two consecutive words Rn Center 32 bits of Rm and Rn Rn
SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn
32 RENESAS
Table 2.13 Arithmetic Instructions
Instruction ADD ADD ADDC ADDV Rm,Rn #imm,Rn Rm,Rn Rm,Rn Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 0011nnnnmmmm0011 0011nnnnmmmm0110 0011nnnnmmmm0111 0100nnnn00010001 0100nnnn00010101 0010nnnnmmmm1100 Operation Rn + Rm Rn Rn + imm Rn Rn + Rm + T Rn, Carry T Rn + Rm Rn, Overflow T If R0 = imm, 1 T If Rn = Rm, 1 T Execution Cycles 1 1 1 1 1 1 T bit -- -- Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0 --
CMP/EQ #imm,R0 CMP/EQ Rm,Rn CMP/HS Rm,Rn CMP/GE Rm,Rn CMP/HI Rm,Rn CMP/GT Rm,Rn CMP/PZ Rn CMP/PL Rn CMP/STR Rm,Rn
If RnRm with 1 unsigned data, 1 T If Rn Rm with signed data, 1 T 1
If Rn > Rm with 1 unsigned data, 1 T If Rn > Rm with signed data, 1 T If Rn 0, 1 T If Rn > 0, 1 T If Rn and Rm have an equivalent byte, 1 T Single-step division (Rn/Rm) MSB of Rn Q, MSB of Rm M, M^QT 0 M/Q/T A byte in Rm is signextended Rn 1 1 1 1
DIV1 DIV0S
Rm,Rn Rm,Rn
0011nnnnmmmm0100 0010nnnnmmmm0111
1 1
DIV0U EXTS.B Rm,Rn
0000000000011001 0110nnnnmmmm1110
1 1
RENESAS33
Table 2.13 Arithmetic Instructions (cont)
Instruction EXTS.W Rm,Rn EXTU.B Rm,Rn EXTU.W Rm,Rn MAC.W @Rm+,@Rn+ Instruction Code 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 0100nnnnmmmm1111 Operation Execution Cycles T bit -- -- -- --
A word in Rm is sign- 1 extended Rn A byte in Rm is zeroextended Rn 1
A word in Rm is zero- 1 extended Rn Signed operation of (Rn) x (Rm) + MAC MAC Signed operation of Rn x Rm MAC Unsigned operation of Rn x Rm MAC 0-Rm Rn 0-Rm-T Rn, Borrow T Rn-Rm Rn Rn-Rm-T Rn, Borrow T Rn-Rm Rn, Underflow T 3/(2)*
MULS MULU NEG NEGC SUB SUBC SUBV
Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn
0010nnnnmmmm1111 0010nnnnmmmm1110 0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011
1-3* 1-3* 1 1 1 1 1
-- -- -- Borrow -- Borrow Underflow
Note: The normal minimum number of execution cycles (The number in parenthesis in the number of cycles when there is contension with preceding/following instructions).
34 RENESAS
Table 2.14 Logic Operation Instructions
Instruction AND AND AND.B NOT OR OR OR.B TAS.B TST TST TST.B XOR XOR XOR.B Rm,Rn #imm,R0 #imm,@(R0,GBR) Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) @Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) Rm,Rn #imm,R0 #imm,@(R0,GBR) Instruction Code Operation Executio n Cycles 1 1 3 1 1 1 3 4 1 1 3 1 1 3 T bit -- -- -- -- -- -- -- Test result Test result Test result Test result -- -- --
0010nnnnmmmm1001 Rn & Rm Rn 11001001iiiiiiii R0 & imm R0 11001101iiiiiiii (R0 + GBR) & imm (R0 + GBR) 0110nnnnmmmm0111 ~Rm Rn 0010nnnnmmmm1011 Rn | Rm Rn 11001011iiiiiiii R0 | imm R0 11001111iiiiiiii (R0 + GBR) | imm (R0 + GBR) 0100nnnn00011011 If (Rn) is 0, 1 T; 1 MSB of (Rn) 0010nnnnmmmm1000 Rn & Rm; if the result is 0, 1 T 11001000iiiiiiii R0 & imm; if the result is 0, 1 T 11001100iiiiiiii (R0 + GBR) & imm; if the result is 0, 1 T 0010nnnnmmmm1010 Rn ^ Rm Rn 11001010iiiiiiii R0 ^ imm R0 11001110iiiiiiii (R0 + GBR) ^ imm (R0 + GBR)
RENESAS35
Table 2.15 Shift Instructions
Instruction ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnn00100000 0100nnnn00100001 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 Operation T Rn MSB LSB Rn T T Rn T T Rn T T Rn 0 MSB Rn T T Rn 0 0 Rn T Rn<<2 Rn Rn>>2 Rn Rn<<8 Rn Rn>>8 Rn Rn<<16 Rn Rn>>16 Rn Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T bit MSB LSB MSB LSB MSB LSB MSB LSB -- -- -- -- -- --
SHLL16 Rn SHLR16 Rn
Table 2.16 Branch Instructions
Instruction BF BT label label Instruction Code Operation Executio n Cycles T bit 3/1* 3/1* 2 2 2 2 2 -- -- -- -- -- -- --
10001011dddddddd If T = 0, dispx2 + PC PC; if T = 1, nop 10001001dddddddd If T = 1, dispx2 + PC PC; if T = 0, nop 1010dddddddddddd Delayed branch, dispx2 + PC PC 1011dddddddddddd Delayed branch, PC PR, dispx2 + PC PC 0100mmmm00101011 Delayed branch, Rm PC 0100mmmm00001011 Delayed branch, PC PR, Rm PC 0000000000001011 Delayed branch, PR PC
BRA label BSR label JMP @Rm JSR @Rm RTS
Note: The execution state is three cycles when program branches, and one cycle when program does not branch.
36 RENESAS
Table 2.17 System Control Instructions
Instruction CLRT CLRMAC LDC LDC LDC LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L NOP RTE SETT SLEEP STC STC STC STC.L STC.L STC.L STS STS STS SR,Rn GBR,Rn VBR,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn MACH,Rn MACL,Rn RR,Rn Rm,SR Rm,GBR Rm,VBR @Rm+,SR @Rm+,GBR @Rm+,VBR Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR Instruction Code Operation Execution Cycles 1 1 1 1 1 3 T bit 0 -- LSB -- -- LSB -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- -- -- -- --
0000000000001000 0 T 0000000000101000 0 MACH, MACL 0100mmmm00001110 Rm SR 0100mmmm00011110 Rm GBR 0100mmmm00101110 Rm VBR 0100mmmm00000111 (Rm) SR, Rm + 4 Rm 0100mmmm00100111 (Rm) VBR, Rm + 4 Rm 0100mmmm00001010 Rm MACH 0100mmmm00011010 Rm MACL 0100mmmm00101010 Rm PR 0100mmmm00000110 (Rm) MACH, Rm + 4 Rm 0100mmmm00010110 (Rm) MACL, Rm + 4 Rm 0100mmmm00100110 (Rm) PR, Rm + 4 Rm 0000000000001001 No operation 0000000000101011 Delayed branch, stack area PC/SR 0000000000011000 1 T 0000000000011011 Sleep 0000nnnn00000010 SR Rn 0000nnnn00010010 GBR Rn 0000nnnn00100010 VBR Rn 0100nnnn00000011 Rn-4 Rn, SR (Rn) 0100nnnn00010011 Rn-4 Rn, GBR (Rn) 0100nnnn00100011 Rn-4 Rn, VBR (Rn) 0000nnnn00001010 MACH Rn 0000nnnn00011010 MACL Rn 0000nnnn00101010 PR Rn
0100mmmm00010111 (Rm) GBR, Rm + 4 Rm 3 3 1 1 1 1 1 1 1 4 1 3* 1 1 1 2 2 2 1 1 1
Note: The number of execution states before the chip enters the sleep state.
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Table 2.17 System Control Instructions (cont)
Instruction STS.L STS.L STS.L TRAPA MACH,@-Rn MACL,@-Rn PR,@-Rn #imm Instruction Code Operation Execution Cycles 1 1 1 8 T bit -- -- -- --
0100nnnn00000010 Rn-4 Rn, MACH (Rn) 0100nnnn00010010 Rn-4 Rn, MACL (Rn) 0100nnnn00100010 Rn-4 Rn, PR (Rn) 11000011iiiiiiii PC/SR stack area, (immx4+VBR) PC
Note: Instruction execution cycles: The execution cycles shown in the table are minimums. The actual number of cycles may be increased: 1. When contention occurs between instruction fetches and data access, or 2. When the destination register of the load instruction (memory register) and the register used by the next instruction are the same.
38 RENESAS
2.4.2
Operation Code Map
Table 2.18 is an operation code map. Table 2.18 Operation Code Map
Instruction Code MSB 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn Fx Fx Fx Fx Rm 0000 0001 0010 STC 0011 01MD MOV.B RM, @(R0,Rn) 1000 CLRT 1001 NOP 1010 1011 RTS 1000 1001 1010 STS 1011 11MD MOV.B @(R0,Rm),Rn disp 00MD MOV.B Rm,@Rn 10MD TST Rm,Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MACH,Rn STS MACL,Rn STS PR,Rn SLEEP RTE MOV.W RM, @(R0,Rn) SETT DIVOU MOV.L RM, @(R0,Rn) CLRMAC SR,Rn STC GBR,Rn STC VBR,Rn Fx: 0000 LSBMD: 00 Fx: 0001 MD: 01 Fx: 0010 MD: 10 Fx: 0011-1111 MD: 11
0000 0000 Fx 0000 0000 Fx 0000 0000 Fx 0000 0000 Fx 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0001 Rn 0010 Rn 0010 Rn 0010 Rn 0010 Rn 0011 Rn 0011 Rn 0011 Rn 0011 Rn 0100 Rn 0100 Rn 0100 Rn Fx Fx Fx Rm Rm Rm Rm Rm Rm Rm Rm Rm Rm Rm Fx Fx Fx
MOV.L Rm,@(disp:4,Rn) MOV.W Rm,@Rn MOV.L Rm,@Rn
01MD MOV.B Rm,@-Rn MOV.W Rm,@-Rn MOV.L Rm,@-Rn DIV0S Rm,Rn AND Rm,Rn XOR MULU Rm,Rn Rm,Rn OR MULS Rm,Rn Rm,Rn 11MD CMP/STR Rm,Rn 00MD CMP/EQ Rm,Rn 01MD DIV1 10MD SUB 11MD ADD 0000 SHLL 0001 SHLR Rm,Rn Rm,Rn Rm,Rn Rn Rn CMP/PZ Rn STS.L MACL, @-Rn XTRCT Rm,Rn
CMP/HS Rm,Rn CMP/HI Rm,Rn SUBC ADDC SHAL SHAR Rm,Rn Rm,Rn Rn Rn
CMP/GE Rm,Rn CMP/GT Rm,Rn SUBV ADDV Rm,Rn Rm,Rn
0010 STS.L MACH, @-Rn
STS.L PR, @-Rn
RENESAS39
Table 2.18 Operation Code Map (cont)
Instruction Code MSB 0100 Rn 0100 Rn 0100 Rn 0100 Rm 0100 Rm 0100 Rn 0100 Rn 0100 Rm 0100 Rm 0100 Rm 0100 Rn 0100 Rn 0101 Rn 0110 Rn 0110 Rn Fx Fx Fx Fx Fx Fx Fx Fx Fx Fx Fx Fx: 0000 LSB MD: 00 0011 STC.L SR,@-Rn 0100 ROTL 0101 ROTR Rn Rn CMP/PL Rn LDS.L @Rm+,MACL LDC.L @Rm+,GBR SHLL8 Rn SHLR8 Rn Fx: 0001 MD: 01 STC.L GBR,@-Rn Fx: 0010 MD: 10 STC.L VBR,@-Rn ROTCL Rn ROTCR Rn LDS.L @Rm+,PR LDC.L @Rm+,VBR SHLL16 Rn SHLL16 Rn Rm,PR @Rm Fx: 0011-1111 MD: 11
0110 LDS.L @Rm+,MACH 0111 LDC.L @Rm+,SR 1000 SHLL2 Rn 1001 SHLR2 Rn 1010 LDS 1011 JSR 1100 1101 1110 LDC Rm,Sr @Rm
Rm,MACH LDS
Rm,MACL LDS JMP
0100 Rm/Rn Fx
TAS.B @Rn
LDC
Rm,GBR LDC
Rm,VBR
Rm 1111 MAC.W @Rm+,@Rn+ Rm disp MOV.L @(disp:4,Rm),Rn Rm,Rn Rm,Rn Rm 00MD MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV Rm 01MD MOV.B @Rm+,R n n SWAP.W @Rm+,Rn EXTU.W Rm,Rn MOV.W @Rm+,R n NEGC Rm,Rn NEG Rm,Rn MOV.L @Rm+,R NOT
0110 Rn 0110 Rn 0111 Rn
Rm 10MD SWAP.B @Rm+,Rn Rm 11MD EXTU.B Rm,Rn imm disp ADD
EXTS.B Rm,Rn
EXTS.W Rm,Rn
#imm:8,Rn
1000 00MD Rn
MOV.B R0, MOV.W R0, @(disp:4,Rn) @(disp:4,Rn) MOV.B @(disp:4, Rm),R0 MOV.W R0, @(disp:4, Rn),R0 BT disp:8 BF disp:8
1000 01MD Rm disp
1000 10MD 1000 11MD 1001 Rn 1010 1011
imm/disp CMP/EQ #imm:8,R0 imm/disp disp disp disp
MOV.W @(disp:8,PC),Rn BRA BSR disp:12 disp:12
40 RENESAS
Table 2.18 Operation Code Map (cont)
Instruction Code MSB 1100 00MD 1100 01MD imm/disp disp Fx: 0000 LSB MD: 00 Fx: 0001 MD: 01 Fx: 0010 MD: 10 Fx: 0011-1111 MD: 11
MOV.B R0,@ MOV.W R0,@ MOV.L R0,@ TRAPA #imm:8 (disp:8,GBR) (disp:8,GBR) (disp:8,GBR) MOV.B @(disp:8, GBR),R0 TST #imm:8,R0 TST.B #imm:8, @(R0,GBR) MOV.W @(disp:8, GBR),R0 AND #imm:8,R0 AND.B #imm:8, @(R0,GBR) MOV.L @(disp:8, GBR),R0 XOR #imm:8,R0 XOR.B #imm:8, @(R0,GBR) MOVA @(disp:8, PC),R0 OR #imm:8,R0 OR.B #imm:8, @(R0,GBR)
1100 10MD 1100 11MD
imm imm
1101 Rn 1110 Rn 1111 ...
disp imm
MOV.L @(disp:8,PC),Rn MOV #imm:8,Rn
2.5
2.5.1
CPU State
State Transitions
The CPU has five processing states: reset, exception processing, bus release, program execution and power-down. The transitions between the states are shown in figure 2.6. For more information on the reset and exception processing states, see section 4, Exception Processing. For details on the power-down states, see section 19, Power Down States.
RENESAS41
From any state when RES = 0 and NMI = 1
From any state when RES = 0 and NMI = 0 RES = 0, NMI = 0
Power-on reset state RES = 0, NMI = 1 RES = 1, NMI = 1
Manual reset state
When an interrupt source or DMA address error occurs
RES = 1, NMI = 0
Reset states
Exception processing state
Bus request cleared Bus request generated Exception processing source occurs
NMI interrupt source occurs Exception processing ends
Bus release state
Bus request generated
Bus request cleared
Bus request generated Bus request cleared
Program execution state SBY bit set for SLEEP instruction
SBY bit cleared for SLEEP instruction
Sleep mode
Standby mode
Power-down state
Figure 2.6 Transitions Between Processing States Reset State: In the reset state the CPU is reset. This occurs when the RES pin level goes low. When the NMI pin is high, the result is a power-on reset; when it is low, a manual reset will occur.When turning on the power, make sure to carry out a power-on reset.
42 RENESAS
On a power-on reset, all CPU internal states and on-chip peripheral module registers are initialized. In a manual reset, all CPU internal states and on-chip peripheral module registers, with the exception of the bus state controller (BSC) and pin function controller (PFC), are initialized. On a manual reset, the BSC is not initialized, so the refresh operation will continue. Exception Processing State: Exception processing is a transient state that occurs when the CPU's processing state flow is altered by exception processing sources such as resets or interrupts. For a reset, the initial values of the program counter PC (execution start address) and stack pointer SP are fetched from the exception processing vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception processing vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. Program Execution State: In the program execution state, the CPU sequentially executes the program. Power-Down State: In the power-down state, the CPU operation halts and power consumption declines. The SLEEP instruction places the CPU in the power-down state. This state has two modes: sleep mode and standby mode. This is described in more detail in section 2.5.1, PowerDown State. Bus Release State: In the bus release state, the CPU releases rights to the bus to the device that has requested them. 2.5.2 Power-Down State
In addition to the ordinary program execution states, the CPU also has a power-down state in which CPU operation halts and power consumption is lowered. There are two power-down state modes: sleep mode and standby mode. Sleep Mode: When the standby bit SBY (in the standby control register SBYCR) is cleared to 0 and a SLEEP instruction executed, the CPU moves from program execution state to sleep mode. In the sleep mode, the CPU halts and the contents of its internal registers and the data in on-chip RAM are stored. The on-chip peripheral modules other than the CPU do not halt in the sleep mode. To return from sleep mode, use a reset, any interrupt, or a DMA address error; the CPU returns to ordinary program execution state through the exception processing state.
RENESAS43
Software Standby Mode: To enter the standby mode, set the standby bit SBY (in the standby control register SBYCR) to 1 and execute a SLEEP instruction. In standby mode, all CPU, on-chip peripheral module and oscillator functions are halted. CPU internal register contents and on-chip RAM data are held. To return from standby mode, use a reset or an external NMI interrupt. For resets, the CPU returns to ordinary program execution state through the exception processing state when placed in a reset state during oscillator stabilization time. For NMI interrupts, the CPU returns to ordinary program execution state through the exception processing state after the oscillator stabilization time has elapsed. In this mode, power consumption drops markedly, since the oscillator stops. Table 2.19 Power-Down State
State On-chip CPU Peripheral RegiClock CPU Modules sters RAM I/O Ports Halt Run Held Held Held
Mode Sleep mode
Conditions
Canceling 1. Interrupt 2. DMA address error 3. Power-on reset 4. Manual reset
Execute SLEEP Run instruction with SBY bit cleared to 0 in SBYCR
Stand by mode
Execute SLEEP Halt instruction with SBY bit set to 1 in SBYCR
Halt Halt and initialize*
Held
Held Held or 1. NMI high-Z* 2. Power-on (selectable) reset 3. Manual reset
Note: Differs depending on the peripheral module and pin.
44 RENESAS
Section 3 Operating Modes
3.1 Types of Operating Modes and Their Selection
The SH7020 and SH7021 operate in one of four operating modes (modes 0, 1, 2, and 7). Modes 0 and 1 differ in the bus width of memory area 0. The mode is selected by the mode pins (MD2- MD0) as indicated in table 3.1. Do not change the mode selection while the chip is operating. Table 3.1 Operating Mode Selection
Pin Settings Operating Mode Mode 0* Mode 1* Mode 2 Mode 7*
2 2
MD2 0 0 0 1
MD1 0 0 1 1
MD0 0 1 0 1
Mode Name MCU mode 0 MCU mode 1 MCU mode 2 PROM mode
Bus Width of Area 0 8 bits 16 bits On-chip ROM --
Notes : 1.SH7021 PROM version only 2.Only modes 0 and 1are available in the SH7020 ROMless version.
3.2
3.2.1
Operating Mode Descriptions
Mode 0 (MCU Mode 0)
In mode 0, memory area 0 has an eight-bit bus width. For the memory map, see section 8, Bus State Controller. 3.2.2 Mode 1 (MCU Mode 1)
In mode 1, memory area 0 has a 16-bit bus width. 3.2.3 Mode 2 (MCU Mode 2)
In mode 2, memory area 0 is assigned to the on-chip ROM. 3.2.4 Mode 7 (PROM Mode)
Mode 7 is a PROM mode. In this mode, the EPROM can be programmed.For details,see section 16, ROM. Do not set to mode 7 unless the product is the SH7021(PROM version).
RENESAS 45
Section 4 Exception Processing
4.1
4.1.1
Overview
Exception Processing Types and Priorities
As figure 4.1 indicates, exception processing may be caused by a reset, address error, interrupt, or instruction. Exception sources are prioritized as indicated in figure 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in the priority order shown.
RENESAS 47
Priority Reset * Power-on reset * Manual reset * CPU address error * DMA address error High
Address error
* NMI * User break * IRQ Interrupt Exception source
* IRQ0-IRQ7 * Direct memory access controller * 16-bit integrated-timer pulse unit * Serial communications interface * Parity control unit (part of the bus controller) * Watchdog timer * DRAM refresh control unit (part of the bus controller)
* On-chip module
* Trap instruction Instruction * General illegal instruction * Illegal slot instruction
* TRAPA instruction * Undefined code * Undefined instruction or instruction that rewrites the PC*1 Low placed directly after a delayed branch instruction*2
Notes: 1. 2.
The instructions that rewrite the PC are JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, and TRAPA. The delayed branch instructions are JMP, JSR. BRA. BSR, RTS, and RTE.
Figure 4.1 Exception Source Types and Priority
48 RENESAS
4.1.2
Exception Processing Operation
Exception sources are detected at the times indicated in table 4.1, whereupon processing starts. Table 4.1 Exception Source Detection and Time of the Start of Processing
Source Detection and Time of the Start of Processing Low-to-high transition at pin RES when NMI is high Low-to-high transition at pin RES when NMI is low Detected when instruction is decoded and starts after the instruction that was executing prior to this point is completed. Detected when instruction is decoded and starts after the instruction that was executing prior to this point is completed. Trap instruction Starts when a trap instruction (TRAPA) is executed. General illegal instruction Illegal slot instruction Starts when undefined code is decoded at a position other than directly after a delayed branch instruction (a delay slot). Starts when undefined code or an instruction that rewrites the PC is decoded directly after a delayed branch instruction (in a delay slot).
Exception Type Reset Power-on Manual Address error Interrupt Instruction
When exception processing begins, the CPU operates as follows: Resets: The initial values of the program counter (PC) and stack pointer (SP) are read from the exception vector table (the respective PC and SP values are H'00000000 and H'00000004 for a power-on reset and H'00000008 and H'0000000C for a manual reset). For more information on the exception vector table, see section 4.1.3, Exception Vector Table. Next, the vector base register (VBR) is cleared to zero and interrupt mask bits (I3-I0) in the status register (SR) are set to 1111. Program execution starts from the PC address read from the exception vector table. Address Errors, Interrupts and Instructions: SR and PC are pushed onto the stack indicated in R15. For interrupts, the interrupt priority level is written in the interrupt mask bits (I3-I0). For address errors and instructions, bits I3-I0 are not affected. Next, the start address is fetched from the exception vector table, and program execution starts from this address. 4.1.3 Exception Process Vector Table
Before exception processing can execute, the exception vector table must be set in memory. The exception processing vector table holds the start addresses of exception service routines (the table for reset exception processing stores initial PC and SP values). Different vector numbers and vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the corresponding vector numbers and vector address offsets. In exception processing, the exception service routine start address is fetched from the exception vector table indicated by this vector table address.
RENESAS 49
Table 4.2 lists vector numbers and vector table address offsets. Table 4.3 shows how to calculate vector table addresses. Table 4.2 Exception Process Vector Table
Vector Number PC SP Manual reset PC SP General illegal instruction (Reserved for system use) Illegal slot instruction (Reserved for system use) 0 1 2 3 4 5 6 7 8 CPU address error DMA address error Interrupts NMI User break (Reserved for system use) Trap instruction (user vectors) Interrupts IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 On-chip modules* 9 10 11 12 13-31 32-63 64 65 66 67 68 69 70 71 72-255 Vector table Address Offset H'00000000-H'00000003 H'00000004-H'00000007 H'00000008-H'0000000B H'0000000C-H'0000000F H'00000010-H'00000013 H'00000014-H'00000017 H'00000018-H'0000001B H'0000001C-H'0000001F H'00000020-H'00000023 H'00000024-H'00000027 H'00000028-H'0000002B H'0000002C-H'0000002F H'00000030-H'00000033 H'00000034-H'00000037 to H'0000007C- H'0000007F H'00000080-H'00000083 to H'000000FC- H'000000FF H'00000100-H'00000103 H'00000104-H'00000107 H'00000108-H'0000010B H'0000010C-H'0000010F H'00000110-H'00000113 H'00000114-H'00000117 H'00000118-H'0000011B H'0000011C-H'0000011F H'00000120-H'00000123 to H'000003FC- H'000003FF
Exception Source Power-on reset
Note: See table 5.3, Interrupt Exception Processing Vectors and Rankings, in section 5, Interrupt Controller, for details on vector numbers and vector table address offsets of individual onchip peripheral module interrupts. 50 RENESAS
Table 4.3
Calculation of Exception Vector table Addresses
Calculation of Vector table Addresses (Vector table address) = (vector table address offset) = (vector number) x 4 (Vector table address) = VBR + (vector table address offset) = VBR + (vector number) x 4
Exception Source Reset Address error, interrupt, instructions
Note: VBR: Vector base register. For vector table address offsets and vector numbers, see table 4.2.
4.2
4.2.1
Reset
Reset Types
A reset is the highest-priority exception. There are two types of reset: power-on reset and manual reset. As table 4.4 shows, a power-on reset initializes the internal state of the CPU and all registers of the on-chip peripheral modules. A manual reset initializes the internal state of the CPU and all registers of the on-chip peripheral modules except the bus state controller (BSC), pin function controller (PFC) and I/O ports (I/O). Table 4.4 Reset Types
Transition Conditions Reset Power-on Reset Manual Reset NMI High Low RES Low Low CPU Initialize Initialize Internal State On-Chip Peripheral Module Initialize Initialize all except BSC, PFC and I/O
4.2.2
Power-On Reset
When the NMI pin is high, a low input at the RES pin drives the chip into the power-on reset state. The RES pin should be driven low while the clock pulse generator (CPG) is stopped (or while the CPG is operating during the oscillation settling time) for at least 20 tcyc to assure that the LSI is reset. A power-on reset initializes the internal state of the CPU and all registers of the on-chip peripheral modules. For pin states in the power-on reset state, see appendix B, Pin States. While the NMI pin remains high, if the RES pin is held low for a certain time then driven high in the power-on state, power-on reset exception processing begins. The CPU then: 1. Reads the start address (initial PC value) from the exception vector table. 2. Reads the initial stack pointer value (SP) from the exception vector table.
RENESAS 51
3. Clears the vector base register (VBR) to H'00000000, and sets interrupt mask bits I3-I0 in the status register (SR) to H'F (1111). 4. Loads the values read from the exception vector table into PC and SP and starts program execution. Further, make sure to carry out a power-on reset when turning on the power of the system. 4.2.3 Manual Reset
When the NMI pin is high, a low input at the RES pin drives the chip into the manual reset state. To be assured of resetting the LSI, drive the RES pin low for at least 20 tcyc. A manual reset initializes the internal state of the CPU and all registers of the on-chip peripheral modules except the bus state controller, pin function controller and I/O ports. Since a manual reset does not affect the bus state controller, the DRAM refresh control function operates even if the manual reset state continues for a long time. When a manual reset is performed during the bus cycle, the manual reset exception processing waits for the end of the bus cycle before beginning. The manual reset thus cannot be used to abort the bus cycle. For the pin states during the manual reset state, see appendix B, Pin States. While the NMI pin remains low, if the RES pin is held low for a certain time then driven high in the manual reset state, manual reset exception processing begins. The CPU carries out the same operations as for a power-on reset.
4.3
4.3.1
Address Errors
Address Error Sources
Address errors occur during instruction fetches and data reading/writing as shown in table 4.5.
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Table 4.5
Address Error Sources
Bus Cycle
Type
Bus Master
Operation Instruction fetch from even address Instruction fetch from odd address Instruction fetch from outside on-chip peripheral module space Instruction fetch from on-chip peripheral module space
Address Error None (normal) Address error None (normal) Address error None (normal) Address error None (normal) Address error None (normal) None (normal) Address error
Instruction fetch CPU
Data read/write
CPU or DMAC
Access to word data from even address Access to word data from odd address Access to long word data aligned on long word boundary Access to long word data not aligned on long word boundary Access to word or byte data in on-chip peripheral module space* Access to long word data in 16-bit on-chip peripheral module space* Access to long word data in 8-bit on-chip peripheral module space*
Note: See section 8, Bus State Controller, for details on the on-chip peripheral module space.
4.3.2
Address Error Exception Processing
When an address error occurs, address error exception processing starts after both the bus cycle that caused the address error and the instructions that were being executed at that time have been completed. The CPU then: 1. Pushes the SR onto the stack. 2. Pushes the program counter onto the stack. The PC value saved is the top address of the instruction following the last instruction to be executed. 3. Fetches the exception service routine start address from the exception vector table for the address error that occurred and starts program execution from that address. The branch that occurs here is not a delayed branch.
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4.4
4.4.1
Interrupts
Interrupt Sources
Table 4.6 lists the types of interrupt exception processing sources (NMI, user break, IRQ, on-chip peripheral module). Table 4.6
Interrupt NMI User break IRQ On-chip
Interrupt Sources
Requesting Pin or Module NMI pin (external input) User break controller IRQ0-IRQ7 pin (external input) Direct Memory Access Controller 16-bit integrated-timer pulse unit Serial communications interface Watchdog timer Bus state controller Number of Sources 1 1 8
4
15 8 1 2
Each interrupt source has a different vector number and vector address offset value. See table 5.3, Interrupt Exception Vectors and Rankings, in section 5, Interrupt Controller, for details on vector numbers and vector table address offsets. 4.4.2 Interrupt Priority Rankings
Interrupt sources are assigned priorities. When multiple interrupts occur at the same time, the interrupt controller (INTC) ascertains their priorities and starts exception processing based on its findings. Priorities from 16-0 can be assigned, with 0 the lowest level and 16 the highest. The NMI has priority level 16 and cannot be masked. NMI is always accepted. The user break priority level is 15. The IRQ and on-chip peripheral module interrupt priority levels can be set in interrupt priority level registers A-E (IPRA-IPRE) as shown in table 4.7. Priority levels 0-15 can be set. See section 5.3.1, Interrupt Priority Level Registers A-E (IPRA-IPRE), for details. Table 4.7
Type NMI User break
Interrupt Priority Rankings
Priority 16 15 Comments Fixed and unmaskable Fixed Set in interrupt priority level registers A-E (IPRA-IPRE)
IRQ and on-chip peripheral modules 0-15
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4.4.3
Interrupt Exception Processing
When an interrupt is generated, the INTC ascertains the interrupt rankings. NMI is always accepted, but other interrupts are only accepted if their ranking is higher than the ranking set in the interrupt mask bits (I3-I0) of the SR. When an interrupt is accepted, interrupt exception processing begins. In the interrupt exception processing sequence, the SR and PC are pushed onto the stack, and the priority level of the accepted interrupt is copied to the interrupt mask level bits (I3-I0) in the SR. In NMI exception processing, the priority ranking is 16 but the value 15 (H'F) is stored in I3-I0. The exception service routine start address for the accepted interrupt is fetched from the exception vector table and the program branches to that address and starts executing. For further information on interrupts, see section 5.4, Interrupt Operation.
4.5
4.5.1
Instruction Exceptions
Types of Instruction Exceptions
Table 4.8 shows the three types of instruction that start exception processing (trap instructions, illegal slot instructions, and general illegal instructions). Table 4.8
Type Trap instruction Illegal slot instruction
Types of Instruction Exceptions
Source Instruction TRAPA Undefined code or instruction that rewrites the PC located immediately after a delayed branch instruction (delay slot) Undefined code in other than delayed slot Comments -- Delayed branch instructions are: JMP, JSR, BRA, BSR, RTS, RTE. Instructions that rewrite the PC are: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF and TRAPA --
General illegal instructions
4.5.2
Trap Instruction
Trap instruction exception processing is carried out when a trap instruction (TRAPA) is executed. The CPU then: 1. Saves the status register by pushing register contents onto the stack. 2. Pushes the program counter value onto the stack. The PC value saved is the top address of the next instruction after the TRAPA instruction. 3. Reads an exception processing service routine start address from the vector table corresponding to a vector number specified in the TRAPA instruction, branches to that address, and starts program execution. The branch is not a delayed branch.
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4.5.3
Illegal Slot Instruction
An instruction located immediately after a delayed branch instruction is called an "instruction placed in a delay slot." If an undefined instruction is located in a delay slot, illegal slot instruction exception processing begins executing when the undefined code is decoded. Illegal slot instruction exception processing also begins when the instruction located in the delay slot is an instruction that rewrites the program counter. In this case, exception processing begins when the instruction that rewrites the PC is decoded. The CPU performs illegal slot exception processing as follows: 1. Saves the status register onto the stack. 2. Pushes the program counter value onto the stack. The PC value saved is the branch destination address of the delayed branch instruction immediately before the instruction that contains the undefined code or rewrites the PC. 3. Fetches an exception processing service routine start address from the vector table corresponding to the exception that occurred, branches to that address and the program starts executing. The branch is not a delayed branch. 4.5.4 General Illegal Instructions
If an undefined instruction located other than a delay slot (immediately after a delayed branch instruction) is decoded, general illegal instruction exception processing is executed. The CPU follows the same procedure as for illegal slot exception processing, except that the program counter (PC) value pushed on the stack in general illegal instruction exception processing is the top address of the illegal instruction with the undefined code.
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4.6
Cases in Which Exceptions Are Not Accepted
In some cases, address errors and interrupts that directly follow a delayed branch instruction or interrupt-disabled instruction are not accepted immediately. Table 4.9 lists these cases. When this occurs, the exception is accepted when an instruction that can accept the exception is decoded. Table 4.9 Cases in Which Exceptions Are Not Accepted
Exception Source Case Immediately after delayed branch instruction*1 instruction*2 Address Error X O Interrupt X X
Immediately after interrupt-disabled
X: Not accepted O: Accepted Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE 2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L
4.6.1
Immediately after Delayed Branch Instructions
Address errors and interrupts are not accepted when an instruction in a delay slot immediately following a delayed branch instruction is decoded. The delayed branch instruction and the instruction in the delay slot are therefore always executed one after the other. Exception processing is never inserted between them. 4.6.2 Immediately after Interrupt-Disabling Instructions
Interrupts are not accepted when the instruction immediately following an interrupt-disabled instruction is decoded. Address errors are accepted, however.
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4.7
Stack Status after Exception Processing
Table 4.10 shows the stack after exception processing. Table 4.10 Stack after Exception Processing
Type Address error Stack Status Address of instruction Upper 16 bits after instruction that has finished executing Lower 16 bits SR Upper 16 bits Lower 16 bits Trap instruction Illegal slot instruction SR Type Interrupt Stack Status Address of instruction Upper 16 bits after instruction that has finished executing Lower 16 bits Upper 16 bits Lower 16 bits
SP
SP
SP
Address of instruction Upper 16 bits after TRAPA instruction Lower 16 bits SR Upper 16 bits Lower 16 bits
SP
Branch destination address of delayed branch instuction
Upper 16 bits
Lower 16 bits SR Upper 16 bits Lower 16 bits
General illegal instruction
SP
Start address of illegal instruction
Upper 16 bits
Lower 16 bits SR Upper 16 bits Lower 16 bits Note: Stack status is based on a bus width of 16 bits.
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4.8
4.8.1
Notes
Value of the Stack Pointer (SP)
An address error occurs if the stack is accessed for exception processing when the value of the stack pointer (SP) is not a multiple of four. Therefore, a multiple of four should always be stored in SP. 4.8.2 Value of the Vector Base Register (VBR)
An address error occurs if the vector table is accessed for exception processing when the value of the vector base register (VBR) is not a multiple of four. Therefore, VBR should always be set to a multiple of four. 4.8.3 Address Errors that Are Caused by Stacking During Address Error Exception Processing
When the stack pointer is not a multiple of four, address errors will occur in the exception processing (interrupt, etc.) stacking. After the exception processing ends, the CPU will then shift to address error exception processing. An address error will also occur during the address error exception processing stacking, but the CPU is set up to ignore the address error so that it can avoid an infinite series of address errors. This allows it to shift program control to the address error exception service routine and process the error. When an address error does occur in exception processing stacking, the stacking bus cycle (write) is executed. In SR and PC stacking, four is subtracted from each of the SPs so the SP values are not multiples of four after stacking either. Since the address value output during stacking is the SP value, the address that produced the error is exactly what is output. In such cases, the stacked write data will be undefined.
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Section 5 Interrupt Controller (INTC)
5.1 Overview
The interrupt controller (INTC) determines the priority of interrupt sources and controls interrupt requests to the CPU. INTC has registers for assigning priority levels to interrupt sources. These registers handle interrupt requests according to user-established priorities. 5.1.1 Features
The interrupt controller has the following features: * * 16 settable priority levels: Five interrupt priority registers can set 16 levels of interrupt priorities for IRQ and on-chip peripheral interrupt sources. The INTC has an NMI input level T bit that indicates NMI pin status. By reading this bit with the interrupt exception service routine, the pin status can be checked for use in a noise canceller function. The interrupt controller can notify external devices (via the IRQOUT pin) that an onchip interrupt has been occured. In this way an external device can, for example, be informed if an on-chip interrupt occurs while the chip is operating in a bus-released mode and the bus has been requested. Block Diagram
*
5.1.2
Figure 5.1 is a block diagram of the interrupt controller.
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IRQOUT NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SR UBC DMAC ITU SCI PRT WDT REF (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) I3 I2 I1 I0 Input control
Priority decision logic
Comparator
Interrupt request
CPU
IPR ICR IPRA-IPRE
Module bus
Bus interface
INTC
UBC: User break controller DMAC: Direct memory access controller ITU: 16-bit integrated-timer pulse unit SCI: Serial communications interface PRT: Parity control unit of BSC
WDT: Watchdog timer REF: DRAM refresh control unit of BSC ICR: Interrupt control register IPRA-IPRE: Interrupt priority registers A-E SR: Status register
Figure 5.1 Block Diagram of the Interrupt Controller
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Internal bus
5.1.3
Pin Configuration
INTC pins are summarized in table 5.1. Table 5.1
Name Nonmaskable interrupt input pin Interrupt request input pins Interrupt request output pin
INTC Pin Configuration
Abbr. NMI IRQ0-IRQ7 IRQOUT I/O I I O Function Inputs a non-maskable interrupt request signal Inputs maskable interrupt request signals Outputs a signal indicating an interrupt source has occurred.
5.1.4
Registers
The interrupt controller has six registers as listed in table 5.2. These registers are used for setting interrupt priority levels and controlling the detection of external interrupt input signals. Table 5.2
Name Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt control register Note:
Interrupt Controller Register Configuration
Abbr. IPRA IPRB IPRC IPRD IPRE ICR R/W R/W R/W R/W R/W R/W R/W Address* 2 H'5FFFF84 H'5FFFF86 H'5FFFF88 H'5FFFF8A H'5FFFF8C H'5FFFF8E Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 *1 Bus width 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32
1. H'8000 when pin NMI is high, H'0000 when pin NMI is low. 2. Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Description of Areas.
5.2
Interrupt Sources
There are four types of interrupt sources: NMI, user break, IRQ, and on-chip peripheral module interrupts. Interrupt rankings are expressed as priority levels (0-16), with 0 the lowest and 16 the highest. An interrupt set to level 0 is masked.
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5.2.1
NMI Interrupts
NMI is the highest-priority interrupt (level 16) and is always accepted. Input at the NMI pin is edge-sensed. Either the rising or falling edge can be selected by setting the NMI edge select bit (NMIE) in the interrupt control register (ICR). NMI interrupt exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to level 15. 5.2.2 User Break Interrupt
A user break interrupt occurs when a break condition is satisfied in the user break controller (UBC). A user break interrupt has priority level 15. User break interrupt exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to level 15. For further details about the user break interrupt, see section 6, User Break Controller. 5.2.3 IRQ Interrupts
IRQ interrupts are requested by input from pins IRQ0-IRQ7. IRQ sense select bits 0-7 (IRQ0S- IRQ7S) in the interrupt control register (ICR) can select low-level sensing or falling-edge sensing for each pin independently. Interrupt priority registers A and B (IPRA and IPRB) can select priority levels from 0-15 for each pin. IRQ interrupt exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to the priority level value of the IRQ interrupt that was accepted. 5.2.4 On-Chip Interrupts
On-chip interrupts are interrupts generated by the following 5 on-chip peripheral modules: * * * * * Direct memory access controller (DMAC) 16-bit integrated-timer pulse unit (ITU) Serial communications interface (SCI) Bus state controller (BSC) Watchdog timer (WDT)
A different interrupt vector is assigned to each interrupt source, so the exception service routine does not have to decide which interrupt has occurred. Priority levels 0-15 can be assigned to individual on-chip peripheral module in interrupt priority registers C-E (IPRC-IPRE). On-chip interrupt exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to the priority level value of the on-chip interrupt that was accepted.
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5.2.5
Interrupt Exception Vectors and Priority Rankings
Table 5.3 lists the vector numbers, vector table address offsets, and interrupt priority order of the interrupt sources. Each interrupt source is allocated a different vector number and vector table address offset. The vector table address is calculated from this vector number and address offset. In interrupt exception processing, the exception service routine start address is fetched from the vector table indicated by this vector table address. See table 4.3, Calculation of Exception Vector table Addresses, in section 4, Exception Processing, for details on this calculation. Arbitrary interrupt priority levels between 0 and 15 can be assigned to IRQ and on-chip peripheral module interrupt sources by setting interrupt priority registers A-E (IPRA-IPRE) for each pin or module. The interrupt sources for IPRC-IPRE, however, must be ranked in the order listed under Priority Within Module in table 5.3 and cannot be changed. A reset assigns priority level 0 to IRQ and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources, and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 5.3.
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Table 5.3
Interrupt Exception Vectors and Rankings
Priority VecWithin tor Address Offset in Module No. Vector table -- -- 11 12 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Default Priority Order
Interrupt Priority Order IPR (bit Interrupt Source (initial value) numbers) NMI User break IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 DMAC0 DEI0 Reserved DMAC1 DEI1 Reserved DMAC2 DEI2 Reserved DMAC3 DEI3 Reserved ITU0 IMIA0 IMIB0 OVI0 Reserved ITU1 IMIA1 IMIB1 OVI1 Reserved ITU2 IMIA2 IMIB2 OVI2 Reserved 0-15 (0) 0-15 (0) IPRC (3-0) 0-15 (0) IPRC (7-4) 0-15 (0) IPRC (11-8) 16 15 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) -- --
H'0000002C-H'0000002F High H'00000030-H'00000033 H'00000100-H'00000103 H'00000104-H'00000107 H'00000108-H'0000010B H'0000010C-H'0000010F H'00000110-H'00000113 H'00000114-H'00000117 H'00000118-H'0000011B H'0000011C-H'0000011F H'00000120-H'00000123 H'00000124-H'00000127 H'00000128-H'0000012B H'0000012C-H'0000012F H'00000130-H'00000133 H'00000134-H'00000137 H'00000138-H'0000013B H'0000013C-H'0000013F H'00000140-H'00000143 H'00000144-H'00000147 H'00000148-H'0000014B H'0000014C-H'0000014F H'00000150-H'00000153 H'00000154-H'00000157 H'00000158-H'0000015B H'0000015C-H'0000015F H'00000160-H'00000163 H'00000164-H'00000167 H'00000168-H'0000016B H'0000016C-H'0000016F
IPRA (15-12) -- IPRA (11-8) IPRA (7-4) IPRA (3-0) -- -- --
IPRB (15-12) -- IPRB (11-8) IPRB (7-4) IPRB (3-0) -- -- --
IPRC (15-12) 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 IPRD (15-12) 3 2 1 0
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Table 5.3
Interrupt Exception Vectors and Rankings (cont)
Priority VecWithin tor Address Offset in Module No. Vector table 3 2 1 0 0-15 (0) IPRD (7-4) 3 2 1 0 0-15 (0) IPRD (3-0) 3 2 1 0 0-15 (0) IPRE (15-12) 3 2 1 0 0-15 (0) IPRE (11-8) 3 2 1 0 0-15 (0) IPRE (7-4) 3 2 1 0 -- -- -- 92 93 94 95 96 97 98 99 H'00000170-H'00000173 H'00000174-H'00000177 _ H'00000178-H'0000017B H'0000017C-H'0000017F H'00000180-H'00000183 H'00000184-H'00000187 H'00000188-H'0000018B H'0000018C-H'0000018F Default Priority Order
Interrupt Priority Order IPR (bit Interrupt Source (initial value) numbers) ITU3 IMIA3 IMIB3 OVI3 Reserved ITU4 IMIA4 IMIB4 OVI4 Reserved SCI0 ERI0 RxI0 TxI0 TEI0 SCI1 ERI1 RxI1 TxI1 TEI1 PRT*1 PEI Reserved Reserved Reserved WDT REF*2 ITI CMI Reserved Reserved Reserved 0-15 (0) IPRD (11-8)
100 H'00000190-H'00000193 101 H'00000194-H'00000197 102 H'00000198-H'0000019B 103 H'0000019C-H'0000019F 104 H'000001A0-H'000001A3 105 H'000001A4-H'000001A7 106 H'000001A8-H'000001AB 107 H'000001AC-H'000001AF 108 H'000001B0-H'000001B3 109 H'000001B4-H'000001B7 110 H'000001B8-H'000001BB 111 H'000001BC-H'000001BF 112 H'000001C0-H'000001C3 113 H'000001C4-H'000001C7 114 H'000001C8-H'000001CB 115 H'000001CC-H'000001CF 116 H'000001D0-H'000001D3 to to 255 H'000003FC-H'000003FF Low
Notes: 1. PRT: Parity control unit of bus state controller. 2. REF: DRAM refresh control unit of bus state controller.
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5.3
5.3.1
Register Descriptions
Interrupt Priority Registers A-E (IPRA-IPRE)
The five registers from IPRA-IPRE are 16-bit read/write registers that assign priority levels from 0-15 to the IRQ and on-chip peripheral module interrupt sources. Interrupt request sources are mapped onto IPRA-IPRE as shown in table 5.4.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 15 14 13 12 11 10 9 8
Table 5.4
Register IPRA IPRB IPRC IPRD IPRE
Interrupt Request Sources and IPRA-IPRE
Bits 15-12 IRQ0 IRQ4 DMAC0, DMAC1 ITU2 SCI1 Bits 11-8 IRQ1 IRQ5 DMAC2, DMAC3 ITU3 PRT*1 Bits 7-4 IRQ2 IRQ6 ITU0 ITU4 WDT, REF*2 Bits 3-0 IRQ3 IRQ7 ITU1 SCI0 (Reserved)*3
Notes: 1. PRT: Parity control unit of bus state controller. See section 8, Bus State Controller, for details. 2. REF: DRAM refresh control unit of bus controller. See section 8, Bus State Controller, for details. 3. When read, always 0. Always write 0 in reserved bits.
As indicated in table 5.4, four IRQ pins or four groups of on-chip peripheral modules are assigned to each interrupt priority register. The priority levels for the four pins or groups can be set by setting the corresponding 4-bit groups of bits 15-12, bits 11-8, bits 7-4, and bits 3-0 (of IPRA- IPRE) with values in the range of H'0 (0000) to H'F (1111). Setting H'0 gives interrupt priority level 0 (the lowest). Setting H'F gives level 15 (the highest). When two on-chip peripheral modules are assigned to the same bits (DMAC0 and DMAC1, or DMAC2 and DMAC3, or the watchdog timer and DRAM refresh control unit), those two modules have the same priority. A reset initializes IPRA-IPRE to H'0000. They are not initialized by the standby mode.
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5.3.2
Interrupt Control Register (ICR)
ICR is a 16-bit register that sets the input detection mode of the external interrupt input pins NMI and IRQ0-IRQ7 and indicates the input signal level to the NMI pin. A reset initializes ICR but the standby mode does not.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 NMIL * R 7 IRQ0S 0 R/W 14 -- 0 -- 6 IRQ1S 0 R/W 13 -- 0 -- 5 IRQ2S 0 R/W 12 -- 0 -- 4 IRQ3S 0 R/W 11 -- 0 -- 3 IRQ4S 0 R/W 10 -- 0 -- 2 IRQ5S 0 R/W 9 -- 0 -- 1 IRQ6S 0 R/W 8 NMIE 0 R/W 0 IRQ7S 0 R/W
Note: When NMI input is high: 1; when NMI input is low: 0
*
Bit 15 (NMI input level (NMIL)): NMIL sets the level of the signal input at the NMI pin. NMIL cannot be modified. The NMI input level can be read to determine the NMI pin level.
Description NMI input level is low NMI input level is high
Bit 15: NMIL 0 1
* *
Bits 14-9 (reserved): These bits always read as 0. The write value should always be 0. Bit 8 (NMI edge select (NMIE)): NMIE selects whether the falling or rising edge of the interrupt request signal to the NMI pin is sensed.
Description Interrupt is requested on falling edge of NMI input (initial value) Interrupt is requested on rising edge of NMI input
Bit 8: NMIE 0 1
Bits 7-0 (IRQ0-IRQ7 sense select (IRQ0S-IRQ7S)): IRQ0-IRQ7 select whether the falling edge or low level of the IRQ inputs is sensed at the pins IRQ0-IRQ7. Bits 7-0: IRQ0S-IRQ7S 0 1 Description Interrupt is requested when IRQ input is low (initial value) Interrupt is requested on falling edge of IRQ input
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5.4
5.4.1
Interrupt Operation
Interrupt Sequence
The sequence of interrupt operations will be explained below. Figure 5.2 is a flowchart of the operations up to acceptance of the interrupt. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt in the interrupt requests sent, following the priority order indicated in table 5.3 and the levels set in interrupt priority registers A-E (IPRA-IPRE). Lower priority interrupts are ignored*. If two interrupts with the same priority level are requested simultaneously or if there are multiple interrupts occurring within a single module, the interrupt with the highest default priority or priority within module as indicated in table 5.3 is selected. 3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask level bits (I3-I0) in the CPU's status register (SR). If the request priority level is equal to or less than the interrupt mask level, the request is ignored. If the request priority level is higher than the interrupt mask level, the interrupt controller accepts the request and sends an interrupt request signal to the CPU. 4. When the interrupt controller accepts an interrupt request, it drives the pin IRQOUT low. 5. The CPU detects the interrupt request sent from the interrupt controller when it decodes the next instruction to be executed. Instead of executing that instruction, the CPU starts interrupt exception processing. 6. In interrupt exception processing, first SR and PC are pushed onto the stack. 7. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3-I0) in the status register (SR). 8. When the accepted interrupt is level-sensed or from an on-chip peripheral module, The pin IRQOUT returns to the high level. If the accepted interrupt is edge-sensed, the pin IRQOUT returns to the high level when the instruction to be executed by the CPU in (5) is replaced by the interrupt exception processing. If the interrupt controller has accepted another interrupt (of a level higher than the current interrupt), however, the pin IRQOUT remains low. 9. The CPU accesses the exception vector table at the entry for the vector number of the accepted interrupt, reads the start address of the exception service routine, branches to that address, and starts executing the program there. This branch is not delayed. Note: A request for an external interrupt (IRQ) designated as edge-detected is held pending once only. An external interrupt designated as level-detected is held pending as long as the interrupt request continues, but if the request is cleared before the CPU next accepts an interrupt, the interrupt request is regarded as not having been made. Interrupt requests from on-chip supporting modules are level requests. When the status flag in a particular module is set, an interrupt is requested. For details, see the descriptions of the individual modules. Note that the interrupt request will be continued unless an
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operation described in "Clearing Conditions" is performed.
Program execution state
Interrupt? Yes NMI? Yes
No
No
User break? Yes
No
Level 15 interrupt? Yes
No
Level 14 interrupt? Yes I3 to I0 level 13? No Yes
No No
Yes
I3 to I0 level 14? No Yes
Level 1 interrupt? Yes I3 to I0 = level 0? No
IRQOUT low *1 Pushes SR onto stack Pushes PC onto stack Copies level of acceptance from I3 to I0 IRQOUT high *2 Reads exception vector table Branches to exception service routine I3 to I0 : Interrupt mask bits of status register Notes : *1. IRQOUT is the same signal as the interrupt request signal to the CPU (Figure 5.1). The pin IRQOUT return to the high level when the interrupt controller has accepted the interrupt of a level higher than the I3 to I0 bits of the status register in the CPU. *2. If the accepted interrupt is edge-sensed, the pin IRQOUT returns to the high level when the instruction to be executed by the CPU is replaced by the interrupt exception processing (before the status register is saved to the stack ). If the interrupt controller has accepted another interrupt of a level higher than the current interrupt. and has requested the interrupt to the CPU, however, the pin IRQOUT remains low.
Figure 5.2 Flowchart of Interrupt Operation
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5.4.2
Stack after Interrupt Exception Processing
Figure 5.3 shows the stack after interrupt exception processing.
Address 4n-8 4n-6 4n-4 4n-2 4n SR PC*2 Upper 16 bits Lower 16 bits Upper 16 bits Lower 16 bits SP*3
Notes: 1. 2. 3.
Bus width is 16 bits. PC stores the top address of the next instruction (return instruction) after the executed instruction. The value of SP must always be a multiple of four.
Figure 5.3 Stack after Interrupt Exception Processing
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5.5
Interrupt Response Time
Table 5.5 indicates the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. Figure 5.4 shows the pipeline when an IRQ interrupt is accepted. Table 5.5 Interrupt Response Time
Number of States Item Interrupt priority decision and comparison with SR mask bit NMI or On-Chip Interrupt 2 IRQ 3 Notes
Wait for completion of X ( 0) sequence currently being executed by CPU
The longest sequence is the interrupt or address error exception processing sequence: X = 4 + m1 + m2 + m3 + m4. If an interruptmasking instruction follows, however, the time may be longer.
Time from interrupt exception processing (saving PC and SR and fetching vector address) until fetching of first instruction of interrupt service routine starts Interrupt response Total Minimum Maximum
5 + m1 + m2 + m3
7 + m1 + m2 + m3 10 11 + 2(m1 + m2 + m3) + m4
8 + m1 + m2 + m3 11 12 + 2(m1 + m2 + m3) + m4 0.50-0.55 s at 20 MHz (m1 = m2 = m3 = m4) 0.90- 0.95 s at 20 MHz
Notes: m1-m4 are the number of states needed for the following memory accesses: m1: SR save cycle (long word write) m2: PC save cycle (long word write) m3: Vector address read cycle (long word read) m4: Fetch top instruction of interrupt service routine
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Interrupt accepted 5 + m1 + m2 + m3 3 m1 m2 1 m3 1
3 IRQ Instruction (instruction replaced by interrupt exception handling) Overrun fetch Interrupt service routine-- first instruction IRQOUT (edge) (level)
FDEEMMEMEE F FDE
When m1 = m2 = m3, the interrupt response time is 11 cycles. F (Instruction fetch) D (Instruction decoding) E (Instruction execution) M (Memory access) Instruction fetched from memory where program is stored. The fetched instruction is decoded. Data operations and address calculations are performed according to the decoded results. Data in memory is accessed.
Note: For the interrupt acceptance timing, see table 4.1, Exception Source Detection and Exception Handling Start Timing, in section 4.1.2, Exception Handling Operation.
Figure 5.4 Example of Pipelining in IRQ Interrupt Acceptance
5.6
Usage Notes
When the following operations are performed in the order shown when a pin to which IRQ input is assigned is designated as a general input pin by the pin function controller (PFC) and inputs a lowlevel signal, the IRQ falling edge is detected, and an interrupt request is detected, immediately after the setting in (b) is performed: * * An interrupt control register (ICR) setting is made so that an interrupt is detected at the falling edge of IRQ. ...... (a) The function of pins to which IRQ input is assigned is switched from general input to IRQ input by a pin function controller (PFC) setting. ...... (b)
Therefore, when switching the pin function from general input pin to IRQ input, the pin function controller (PFC) setting should be changed to IRQ input while the pin to which IRQ input is assigned is high.
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Section 6 User Break Controller (UBC)
6.1 Overview
The user break controller (UBC) simplifies the debugging of user programs. Break conditions are set in the UBC and a user break interrupt request is sent to the CPU in response to the contents of a CPU or DMAC bus cycle. This function can implement an effective self-monitoring debugger, enabling a program to be debugged by itself without using a large in-circuit emulator. 6.1.1 * Features
* *
The following break conditions can be set: Address CPU cycle or DMA cycle Instruction fetch or data access Read or write Operand size (long word access, word access, or byte access) When break conditions are met, a user break interrupt is generated. A user-created user break interrupt exception routine can then be executed. When a break is set to a CPU instruction fetch, the break occurs just before the fetched instruction. Block Diagram
6.1.2
Figure 6.1 is the block diagram of the user break controller.
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Module bus
Bus interface Internal bus Interrupt request Interrupt controller
BBR
BAMRH BAMRL
BARH BARL
Break condition comparator
User break interrupt generating circuit UBC
BARH, BARL: Break address registers H and L BAMRH, BAMRL: Break address mask registers H and L BBR: Break bus cycle register
Figure 6.1 Block Diagram of the User Break Controller 6.1.3 Register Configuration
The user break controller has five registers as listed in table 6.1. These registers are used for setting break conditions.
76 RENESAS
Table 6.1
Name
User Break Controller Registers
Abbr. BARH BARL BAMRH BAMRL BBR R/W R/W R/W R/W R/W R/W Address* H'5FFFF90 H'5FFFF92 H'5FFFF94 H'5FFFF96 H'5FFFF98 Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 Bus width 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32
Break address register high Break address register low Break address mask register high Break address mask register low Break bus cycle register
Note: Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Description of Areas.
6.2
6.2.1
Register Descriptions
Break Address Registers (BAR)
There are two break address registers--break address register H (BARH) and break address register L (BARL)--that together form a single group. Both are 16-bit read/write registers. BARH stores the upper bits (bits 31-16) of the address of the break condition. BARL stores the lower bits (bits 15-0) of the address of the break condition. A reset initializes both BARH and BARL to H'0000. Neither is initialized in standby mode. BARH: Break address register H.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 BA31 0 R/W 7 BA23 0 R/W 14 BA30 0 R/W 6 BA22 0 R/W 13 BA29 0 R/W 5 BA21 0 R/W 12 BA28 0 R/W 4 BA20 0 R/W 11 BA27 0 R/W 3 BA19 0 R/W 10 BA26 0 R/W 2 BA18 0 R/W 9 BA25 0 R/W 1 BA17 0 R/W 8 BA24 0 R/W 0 BA16 0 R/W
*
BARH Bits 15-0 (break address 31-16 (BA31-BA16)): BA31-BA16 store the upper bit values (bits 31-16) of the address of the break condition.
RENESAS 77
BARL: Break address register L.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 BA15 0 R/W 7 BA7 0 R/W 14 BA14 0 R/W 6 BA6 0 R/W 13 BA13 0 R/W 5 BA5 0 R/W 12 BA12 0 R/W 4 BA4 0 R/W 11 BA11 0 R/W 3 BA3 0 R/W 10 BA10 0 R/W 2 BA2 0 R/W 9 BA9 0 R/W 1 BA1 0 R/W 8 BA8 0 R/W 0 BA0 0 R/W
*
BARL Bits 15-0 (break address 15-0 (BA15-BA0)): BA15-BA0 store the lower bit values (bits 15-0) of the address of the break condition. Break Address Mask Register (BAMR)
6.2.2
The two break address mask registers--break address mask register H (BAMRH) and break address mask register L (BARML)--together form a single group. Both are 16-bit read/write registers. BAMRH determines which of the bits in the break address set in BARH are masked. BAMRL determines which of the bits in the break address set in BARL are masked. A reset initializes BAMRH and BARML to H'0000. They are not initialized in the standby mode. BAMRH: Break address mask register H.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 BAM31 0 R/W 7 BAM23 0 R/W 14 BAM30 0 R/W 6 BAM22 0 R/W 13 BAM29 0 R/W 5 BAM21 0 R/W 12 BAM28 0 R/W 4 BAM20 0 R/W 11 BAM27 0 R/W 3 BAM19 0 R/W 10 BAM26 0 R/W 2 BAM18 0 R/W 9 BAM25 0 R/W 1 BAM17 0 R/W 8 BAM24 0 R/W 0 BAM16 0 R/W
*
BAMRH bits 15-0 (break address mask 31-16 (BAM31-BAM16)): BAM31-BAM16 specify whether bits BA31-BA16 of the break address set in BARH are masked or not.
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BAMRL: Break address mask register L.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 BAM15 0 R/W 7 BAM7 0 R/W 14 BAM14 0 R/W 6 BAM6 0 R/W 13 BAM13 0 R/W 5 BAM5 0 R/W 12 BAM12 0 R/W 4 BAM4 0 R/W 11 BAM11 0 R/W 3 BAM3 0 R/W 10 BAM10 0 R/W 2 BAM2 0 R/W 9 BAM9 0 R/W 1 BAM1 0 R/W 8 BAM8 0 R/W 0 BAM0 0 R/W
*
BAMRL bits 15-0 (break address mask 15-0 (BAM15-BAM0)): BAM15-BAM0 specify whether bits BA15-BA0 of the break address set in BARH are masked or not.
Description Break address bit BAn is included in the break condition (initial value) Break address bit BAn is not included in the break condition
Bits 15-0: BAMn 0 1 n = 31-0
6.2.3
Break Bus Cycle Register (BBR)
The break bus cycle register (BBR) is a 16-bit read/write register that selects the following four break conditions: * * * * CPU cycle or DMA cycle Instruction fetch or data access Read or write Operand size (byte, word, long word).
A reset initializes BBR to H'0000. It is not initialized in the standby mode.
RENESAS 79
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W:
15 -- 0 -- 7 CD1 0 R/W
14 -- 0 -- 6 CD0 0 R/W
13 -- 0 -- 5 ID1 0 R/W
12 -- 0 -- 4 ID0 0 R/W
11 -- 0 -- 3 RW1 0 R/W
10 -- 0 -- 2 RW0 0 R/W
9 -- 0 -- 1 SZ1 0 R/W
8 -- 0 -- 0 SZ0 0 R/W
* *
Bits 15-8 (reserved): These bits always read as 0. The write value should always be 0. Bits 7 and 6 (CPU cycle/DMA cycle select (CD1 and CD0)): CD1 and CD0 select whether to break on CPU and/or DMA bus cycles.
Bit 6: CD0 0 1 Description No break interrupt occurs (initial value) Break only on CPU cycles Break only on DMA cycles Break on both CPU and DMA cycles
Bit 7: CD1 0
1
0 1
*
Bits 5 and 4 (instruction fetch/data access select (ID1, ID0)): ID1, ID0 select whether to break on instruction fetch and/or data access bus cycles.
Bit 4: ID0 0 1 Description No break interrupt occurs (initial value) Break only on instruction fetch cycles Break only on data access cycles Break on both instruction fetch and data access cycles
Bit 5: ID1 0
1
0 1
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*
Bits 3 and 2 (read/write select (RW1, RW0)): RW1, RW0 select whether to break on read and/or write access cycles.
Bit 2: RW0 0 1 Description No break interrupt occurs (initial value) Break only on read cycles Break only on write cycles Break on both read and write cycles
Bit 3: RW1 0
1
0 1
*
Bits 1 and 0 (operand size select (SZ1, SZ0)): SZ1, SZ0 select bus cycle operand size as a break condition.
Bit 0: SZ0 0 1 Description Operand size is not a break condition (initial value) Break on byte access Break on word access Break on long word access
Bit 1: SZ1 0
1
0 1
Note: When setting to break on an instruction fetch, set the SZ0 bit to 0. All instructions will be considered to be accessed as words (even those instructions in on-chip memory for which two instructions can be fetched simultaneously in a single bus cycle). Instruction fetch is by word access and CPU/DMAC data access is by the specified operand size. They are not determined by the bus width of the space being accessed.
6.3
6.3.1
Operation
Flow of the User Break Operation
The flow from setting of break conditions to user break interrupt exception processing is described below. 1. Break conditions are set in break address register (BAR), break address mask register (BAMR), and the break bus cycle register (BBR). Set the break address in the BAR, the address bits to be masked in the BAMR and the type of breaking bus cycle in the BBR. When even one of the BBR groups (CPU cycle/DMA cycle select bits (CD1, CD0), instruction fetch/data access select bits (ID1, ID0), read/write select bits (RW1, RW0)) is set to 00 (no user break interrupt), there will be no user break even when all other conditions are consistent. To use a user break interrupt, set conditions for all three pairs. 2. The UBC checks to see if the set conditions are satisfied, using the system shown in figure 6.2. When the break conditions are satisfied, the UBC sends a user break interrupt request to the interrupt controller.
RENESAS 81
3. When receiving the user break interrupt request, the interrupt controller checks its priority level. The user break interrupt has priority level 15, so it is accepted only if the interrupt mask level in bits I3-I0 in the status register (SR) is 14 or lower. When the I3-I0 bit level is 15, the user break interrupt cannot be accepted but it is held pending until user break interrupt exception processing is carried out. NMI exception processing sets I3-I0 to level 15, so a user break cannot occur during the NMI service routine unless the NMI service routine itself begins by reducing I3-I0 to level 14 or lower. Section 5, Interrupt Controller, described the handling of priority levels in greater detail. 4. The INTC sends a request signal for a user break interrupt to the CPU. When the CPU receives it, it starts user break interrupt exception processing. Section 5.4, Interrupt Operation, describes interrupt exception processing in more detail.
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BARH/BARL
BAMRH/BAMRL 32
Internal address bits 31-0 CD1
32 32 CD0
32 32
CPU cycle
DMA cycle ID1 ID0
Instruction fetch
User break interrupt
Data access RW1 RW0
Read cycle
Write cycle SZ1 SZ0
Byte size
Word size
Long word size
Figure 6.2 Break Condition Logic
RENESAS 83
6.3.2
Break on Instruction Fetch Cycles to On-Chip Memory
On-chip memory (on-chip ROM and RAM) is always accessed 32 bits each bus cycle. Two instructionsare therefore fetched in a bus cycle from on-chip memory . Although only a single bus cycle occurs for the two-instruction fetch, a break can be set on either instruction by placing the corresponding address in the break address registers (BAR). In other words, to break the second of the two instructions fetched, set its start address in the BAR. The break will then occur after the first instruction executes. 6.3.3 Program Counter (PC) Value Saved in User Break Interrupt Exception Processing
Break on Instruction Fetch: The program counter (PC) value saved in user break interrupt exception processing for an instruction fetch is the address set as the break condition. The user break interrupt is generated before the fetched instruction is executed. If a break condition is set on the fetch cycle of a delayed slot instruction immediately following a delayed branch instruction or on the fetch cycle of an instruction that follows an interrupt-disabling instruction, however, the user break interrupt is not accepted immediately, so the instruction is executed. The user break interrupt is not accepted until immediately after that instruction. The PC value that will be saved is the start address of the next instruction that is able to accept the interrupt. Break on Data Access (CPU/DMAC): The program counter (PC) value is the top address of the next instruction after the last executed instruction at the time when the user break exception processing is activated. When data access (CPU/DMAC) is set as a break condition, the place where the break will occur cannot be specified exactly. The break will occur at the instruction fetched close to where the data access that is to receive the break occurs.
6.4
Setting User Break Conditions
CPU Instruction Fetch Bus Cycle: * Register settings: BARH = H'0000, BARL = H'0404, BBR = H'0054 Conditions set: Address = H'00000404, Bus cycle = CPU, instruction fetch, read (operand size not included in conditions) A user break interrupt will occur immediately before the instruction at address H'00000404. If the instruction at address H'00000402 can accept an interrupt, the user break exception processing will be executed after that instruction is executed. The instruction at H'00000404 will not be executed. The value saved to PC is H'00000404. Register settings: BARH = H'0015, BARL = H'389C, BBR = H'0058 Conditions set: Address = H'0015389C, Bus cycle = CPU, instruction fetch, write (operand size not included in conditions) No user break interrupt occurs, because no instruction fetch cycle is ever a write cycle.
*
84 RENESAS
*
Register settings: BARH = H'0003, BARL = H'0147, BBR = H'0054 Conditions set: Address = H'00030147, Bus cycle = CPU, instruction fetch, read (operand size not included in conditions) No user break interrupt occurs, because instructions are always fetched from even addresses. If the first fetched address after a branch is odd and a user break is set on this address, however, user break exception processing will be carried out after address error exception processing.
CPU Data Access Bus Cycle: * Register settings: BARH = H'0012, BARL = H'3456, BBR = H'006A Conditions set: Address = H'00123456, Bus cycle = CPU, data access, write, word A user break interrupt occurs when word data is written to address H'00123456. Register settings: BARH = H'00A8, BARL = H'0391, BBR = H'0066 Conditions set: Address = H'00A80391, Bus cycle = CPU, data access, read, word No user break interrupt occurs, because word data access is always to an even address.
*
DMA Cycle: * Register setting: BARH = H'0076, BARL = H'BCDC, BBR = H'00A7 Conditions set: Address = H'0076BCDC, Bus cycle = DMA, data access, read, long word A user break interrupt occurs when long word data is read from address H'0076BCDC. Register setting: BARH = H'0023, BARL = H'45C8, BBR = H'0094 Conditions set: Address = H'002345C8, Bus cycle = DMA, instruction fetch, read (operand size not included) No user break interrupt occurs, because a DMA cycle includes no instruction fetch.
*
RENESAS 85
6.5
6.5.1
Notes
On-Chip Memory Instruction Fetch
Two instructions are simultaneously fetched from on-chip memory. If a break condition is set on the second of these two instructions but the contents of the UBC break condition registers are changed so as to alter the break condition immediately after the first of the two instructions is fetched, a user break interrupt will still occur when the second instruction is fetched. 6.5.2 Instruction Fetch at Branches
When a conditional branch instruction or TRAPA instruction causes a branch, instructions are fetched and executed as follows: 1. Conditional branch instruction, branch taken: BT, BF Instruction fetch cycles: Conditional branch fetch Next-instruction overrun fetch Nextinstruction overrun fetch Branch destination fetch Instruction execution: Conditional branch instruction execution Branch destination instruction execution 2. TRAPA instruction, branch taken: TRAPA Instruction fetch cycles: TRAPA instruction fetch Next-instruction overrun fetch Nextinstruction overrun fetch Branch destination fetch Instruction execution: TRAPA instruction execution Branch destination instruction execution When a conditional branch instruction or TRAPA instruction causes a branch, the branch destination will be fetched after the next instruction or the one after that does an overrun fetch. When the next instruction or the one after that is set as a break condition, a branch will result in the generation of a user break interrupt at the next instruction or the instruction after that, neither of which instructions will be executed.
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6.5.3
Instruction Fetch Break
If a break is attempted at the task A return destination instruction fetch, task B is activated before the UBC interrupt by interrupt B generated during task A processing, and the UBC interrupt is handled after the interrupt B exception handling. (1) Cause The SH7032/SH7034 chip operates as follows.
Interrupt B accepted UBC interrupt accepted
Interrupt exception handling
FDEEMMEMEE Interrupt exception handling F

FDE EMMEMEE
0x00011a0a Instruction replaced by interrupt exception handling Break condition 0x00011a0c Overrun fetch 0xf000974 Task B first instruction fetch (instruction replaced by interrupt exception handling) (0xf000978 Overrun fetch) 0x02000030 UBC first instruction fetch
f
F
Figure 6.3
UBC Operation
It actually takes at least two cycles for the UBC interrupt generated by the address 0x00011a0c instruction fetch cycle to be sent to the interrupt controller and interrupt exception handling to begin. However, as shown in figure 6.3, when the UBC interrupt is generated, previously generated interrupt B initiated by task B is accepted first, and the UBC interrupt is accepted after completion of the interrupt B exception handling. (2) Remedy There is no way of preventing this operation by hardware. A software solution, such as the use of a flag, must be employed.
RENESAS 87
Section 7 Clock Pulse Generator (CPG)
7.1 Overview
The SuperH microcomputer has a built-in clock pulse generator (CPG) that supplies the LSI and external devices with a clock pulse. The CPG makes the LSI run at the oscillation frequency of the crystal resonator. The CPG consists of an oscillator and a duty cycle correcting circuit (figure 7.1). The CPG can be made to generate a clock signal by connecting it to a crystal resonator or by inputting an external clock. (The CPG is halted in standby mode.)
CPG
XTAL Oscillator EXTAL CK System clock
Duty correcting circuit
Internal clock ()
Figure 7.1 Block Diagram of the Clock Pulse Generator
7.2
Clock Source
Clock pulses can be supplied from a connected crystal resonator or an external clock. 7.2.1 Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as shown in figure 7.2. Use the damping resistance Rd shown in table 7.1. Use an AT-cut parallel resonating crystal with a frequency equal to the system clock (CK) frequency. Connect load capacitors (C L1 and CL2) as shown in the figure. The clock pulse produced by the crystal resonator and internal pulse generator is sent to the duty cycle correction circuit where its duty cycle is corrected. It is then supplied to the LSI and to external devices.
RENESAS 89
CL1 CL1 = CL2 = IC-22 pF EXTAL Rd XTAL CL2
Figure 7.2 Connection of the Crystal Resonator (Example) Table 7.1 Damping Resistance
2 1k 4 500 8 200 12 0 16 0 20 0
Frequency [MHz] Rd []
Crystal Resonator: Figure 7.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator with the characteristics listed in table 7.2.
L XTAL
CL
Rs EXTAL
C0
Figure 7.3 Crystal Resonator Equivalent Circuit Table 7.2 Crystal Resonator Parameters
Frequency (MHz) Parameter Rs max [] Co max [pF] 2 500 7 4 120 7 8 80 7 12 60 7 16 50 7 20 40 7
Value to be determined (TBD)
7.2.2
External Clock Input
An external clock signal can be input at the EXTAL pin as shown in figure 7.6. The XTAL pin should be left open. The frequency must be equal to the system clock (CK) frequency. The specifications for the waveform of the external clock input are given below. Make the external clock frequency the same as the system clock (CK).
90 RENESAS
Open
XTAL
External clock input
EXTAL
Figure 7.4 External Clock Input Method
tcyc tEXH VIH tEXL
1/2 Vcc VIL
tEXr
tEXf
Figure 7.5 Input Clock Waveform Table 7.3 Input Clock Specifications
5 V Specifications (fmax = 20 MHz) t EXr/f (VIL-VIH) t EXH/L (1/2 VCC standard) Max = 5 Min = 10 3.3 V Specifications (fmax = 12.5 MHz) Max = 10 Min = 20 Units ns ns
7.3
Usage Notes
Board design: When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Route no other signal lines near the XTAL and EXTAL pin signal lines to prevent induction from interfering with correct oscillation. See figure 7.6.
RENESAS 91
No crossing signal lines
CL1
XTAL
CL2
EXTAL
Figure 7.6 Precaution on Oscillator Circuit Board Design Duty cycle correction circuit: Duty cycle corrections are conducted for an input clock over 5 MHz. Duty cycles may not be corrected if under 5 MHz, but AC characteristics for the high-level pulse width (tCH) and low-level pulse width (tCL) of the clock are satisfied, and the LSI will operate normally. Figure 7.7 shows the standard characteristics of a duty cycle correction. This duty cycle correction circuit is not for correcting the input clock's transient fluctuations and jutters.
70 60 50 40 30
Input duty 70 60 50 40 30
Output duty
1
2
5
10
20 (MHz)
Input frequency
Figure 7.7 Duty Cycle Correction Circuit Standard Characteristics
92 RENESAS
Section 8 Bus State Controller (BSC)
8.1 Overview
The bus state controller (BSC) divides address space and outputs control signals for all kinds of memory and peripheral LSIs. BSC functions enable the LSI to link directly with DRAM, SRAM, ROM, and peripheral LSIs without the use of external circuits, simplifying system design and allowing high-speed data transfers in a compact system. 8.1.1 Features
The BSC has the following features. * Address space is divided into eight areas A maximum 4-Mbyte of linear address space for each of eight areas, 0-7 (area 1 can be up to 16-Mbyte linear space when set for DRAM) (The space that can actually be used varies with the type of memory connected) Bus width (8 bits or 16 bits) can be selected by access address On-chip ROM and RAM is accessed in one cycle (32 bits wide) Wait states can be inserted using the WAIT pin Wait state insertion can be controlled through software. Register settings can be used to specify the insertion of 1-4 cycles for areas 0, 2, and 6 (long wait function) The type of memory connected can be specified for each area. Outputs control signals for accessing the memory and peripheral LSIs connected to the area Direct interface to DRAM Multiplexes row/column addresses according to DRAM capacity Two types of byte access signals (dual-CAS system and dual-WE system) Supports burst operation (high-speed page mode) Supports CAS-before-RAS refresh and self-refresh Access control for all memory and peripheral LSIs Address/data multiplex function Parallel execution of external writes and the like with internal access (warp mode) Supports parity check and generation for data bus Odd parity/even parity selectable Interrupt request generated for parity error (PEI interrupt request signal) Refresh counter can be used as an 8-bit interval timer Interrupt request generated at compare match (CMI interrupt request signal) Block Diagram
*
* * *
*
8.1.2
Figure 8.1 shows the block diagram of the bus state controller.
RENESAS 93
Bus interface
WCR1 WAIT Wait control unit WCR2 WCR3 RD WRH, WRL HBS, LBS AH CS7 to CS0 Area control unit Module bus DCR BCR
RCR CASH, CASL RAS CMI interrupt request DRAM control unit RTCSR RTCNT
DPH, DPL PEI interrupt request Peripheral bus Parity control unit
Comparator
RTCOR PCR
Interrupt controller
WCR: Wait state control register BCR: Bus control register DCR: DRAM area control register RCR: Refresh control register
RTCSR: Refresh timer control/status register RTCNT: Refresh timer counter RTCOR: Refresh time constant register PCR: Parity control register
Figure 8.1 BSC Block Diagram
94 RENESAS
Internal bus
8.1.3
Pin Configuration
Table 8.1 shows the BSC pin configuration. Table 8.1
Name Chip select 7-0 Read High write Low write Write High byte strobe Low byte strobe Row address strobe High column address strobe
Pin Configuration
Abbreviation CS7-CS0 RD WRH WRL WR*1 HBS* 2 LBS* 3 RAS CASH I/O Function O O O O O O O O O O O I O Chip select signal that indicates the area being accessed Strobe signal that indicates the read cycle Strobe signal that indicates write cycle to upper 8 bits Strobe signal that indicates write cycle to lower 8 bits Strobe signal that indicates write cycle Strobe signal that indicates access to upper 8 bits Strobe signal that indicates access to lower 8 bits DRAM row address strobe signal Column address strobe signal for accessing the upper 8 bits of the DRAM Column address strobe signal for accessing the lower 8 bits of the DRAM Signal for holding the address for address/data multiplexing Wait state request signal Address output
Low column address CASL strobe Address hold Wait Address bus Data bus Data bus parity high Data bus parity low AH WAIT A21-A0 AD15-AD0 DPH DPL
I/O Data I/O. During address/data multiplexing, address output and data input/output. I/O Parity data I/O for upper byte I/O Parity data I/O for lower byte
Notes: 1. Doubles with the WRL pin. (Selected by the BAS bit of the BCR. See section 8.2.1, Bus Control Register, for details. 2. Doubles with the A0 pin. (Selected by the BAS bit of the BCR. See section 8.2.1, Bus Control Register, for details. 3. Doubles with the WRH pin. (Selected by the BAS bit of the BCR. See section 8.2.1, Bus Control Register, for details.
8.1.4
Register Configuration
The BSC has ten registers (listed in table 8.2) which control space division, wait states, DRAM interface, and parity check.
RENESAS 95
Table 8.2
Name
Register Configuration
Abbr. BCR WCR1 WCR2 WCR3 DCR PCR RCR RTCSR RTCNT RTCOR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'0000 H'FFFF H'FFFF H'F800 H'0000 H'0000 H'0000 H'0000 H'0000 H'00FF Address* 1 H'5FFFFA0 H'5FFFFA2 H'5FFFFA4 H'5FFFFA6 H'5FFFFA8 Bus width 8,16,32 8,16,32 8,16,32 8,16,32 8,16,32
Bus control register Wait state control register 1 Wait state control register 2 Wait state control register 3 DRAM area control register Parity control register Refresh control register Refresh timer control/status register Refresh timer counter Refresh time constant register
H'5FFFFAA 8,16,32 H'5FFFFAC 8,16,32* 2 H'5FFFFAE 8,16,32* 2 H'5FFFFB0 H'5FFFFB2 8,16,32* 2 8,16,32* 2
Notes: 1. Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Description of Areas. 2. Write only with word transfer instructions. See section 8.2.11, Register Access, for details on writing.
8.1.5
Overview of Areas
The SH microprocessors have 32-bit address spaces on the architecture, but the top 4 bits are ignored. Table 8.3 outlines the division of space. As shown, the space is divided into areas 0-7 by the value of the top addresses. Each area is allocated a specific type of space. When the area is accessed, a strobe signal that matches the type of area space is generated. This allocates peripheral LSIs and memory devices according to the type of the area spaces and allows them to be directly linked to this LSI. Some areas are of a fixed type based on their address while others can be selected in registers. Area 0 can be used as an on-chip ROM space or external memory space. Area 1 can be used as DRAM space or external memory space. DRAM space enables direct connection to DRAM and outputs RAS, CAS and multiplexed addresses. Areas 2-4 can only be used as external memory space. Area 5 can be used as on-chip peripheral module space or external memory space. Area 6 can be used as address/data multiplexed I/O space or external memory space. For address/data multiplexed I/O space, an address and data are multiplexed and input/output from AD15-AD0 pins. Area 7 can be used as on-chip RAM space or external memory space. The bus width of the data bus is basically switched between 8 bit and 16 bit by the value of address bit A27. For the following areas, however, the bus width is determined by conditions other than the A27 bit value.
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* * * * *
On-chip ROM space in area 0: Always 32 bits External memory space in area 0: 8 bits when MD0 pin is 0, 16 bits when the pin is 1 On-chip peripheral module space in area 5: 8 bits when the A8 address bit is 0, 16 bits when it is 1 Area 6: If A27 = 0, area 6 is 8 bits when the A14 address bit is 0, 16 bits when A14 is 1 On-chip RAM space in area 7: Always 32 bits
See table 8.6 in section 8.3, Address Space Subdivision, for more information on how the space is divided.
8.2
8.2.1
Register Descriptions
Bus Control Register (BCR)
The bus control register (BCR) is a 16-bit read/write register that selects the functions of areas and status of bus cycles. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or by the standby mode.
Bit: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 0 R/W 7 -- 0 -- 14 IOE 0 R/W 6 -- 0 -- 13 WARP 0 R/W 5 -- 0 -- 12 RDDTY 0 R/W 4 -- 0 -- 11 BAS 0 R/W 3 -- 0 -- 10 -- 0 -- 2 -- 0 -- 9 -- 0 -- 1 -- 0 -- 8 -- 0 -- 0 -- 0 --
Bit name: DRAME
*
Bit 15 (DRAM enable bit (DRAME)): DRAME selects whether area 1 is used as an external memory space or DRAM space. 0 sets it for external memory space and 1 sets it for DRAM space. The setting of the DRAM area control register is valid only when this bit is set to 1.
Description Area 1 is external memory space (initial value) Area 1 is a DRAM space
Bit 15: DRAME 0 1
*
Bit 14 (multiplexed I/O enable bit (IOE)): IOE selects whether area 6 is used as external memory space or an address/data multiplexed I/O area. 0 sets it for external memory space and 1 sets it for address/data multiplexed I/O space. With address/data multiplexed I/O space, address and data are multiplexed and input/output is from AD15-AD0.
RENESAS 97
Bit 14: IOE 0 1
Description Area 6 is external memory space (initial value) Area 6 is an address/data multiplexed I/O area
*
Bit 13 (warp mode bit (WARP)): WARP selects warp or normal mode. 0 sets it for normal mode and 1 sets it for warp mode. In warp mode, some external accesses are carried out in parallel with internal access.
Description Normal mode: External and internal accesses are not simultaneously performed (initial value) Warp mode: External and internal accesses are simultaneously performed
Bit 13: WARP 0 1
*
Bit 12 (RD duty (RDDTY)): RDDTY selects 35% or 50% of the T1 state as the high-level duty cycle ratio of signal RD. 0 sets it for 50%, 1 sets it for 35%. Only set to 1 when the operating frequency is a minimum of 10 MHz.
Description RD signal high-level duty cycle is 50% of T1 state (initial value) RD signal high-level duty cycle is 35% of T1 state
Bit 12: RDDTY 0 1
*
Bit 11 (byte access select (BAS)): BAS selects whether byte access control signals are WRH, WRL, and A0, or LBS, WR and HBS during word space accesses. When this bit is cleared to 0, WRH, WRL, and A0 signals are valid; when set to 1, LBS, WR, and HBS, signals are valid.
Description WRH, WRL, and A0 enabled (initial value) LBS, WR, and HBS enabled
Bit 11: BAS 0 1
*
Bits 10-0 (reserved): These bits always read as 0. The write value should always be 0. Wait State Control Register 1 (WCR1)
8.2.2
Wait state control register 1 is a 16-bit read/write register that controls the number of states for accessing each area and the whether wait states are used. WCR1 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or by the standby mode.
98 RENESAS
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W:
15 RW7 1 R/W 7 -- 1 --
14 RW6 1 R/W 6 -- 1 --
13 RW5 1 R/W 5 -- 1 --
12 RW4 1 R/W 4 -- 1 --
11 RW3 1 R/W 3 -- 1 --
10 RW2 1 R/W 2 -- 1 --
9 RW1 1 R/W 1 WW1 1 R/W
8 RW0 1 R/W 0 -- 1 --
*
Bits 15-8 (wait state control during read (RW7-RW0)): RW7-RW0 determine the number of states in read cycles for each area and whether or not to sample the signal input from the WAIT pin. Bits RW7-RW0 correspond to areas 7-0, respectively. If a bit is cleared to 0, the WAIT signal is not sampled during the read cycle for the corresponding area. If it is set to 1, sampling takes place. For the external memory spaces of areas 1, 3-5, and 7, read cycles are completed in one state when the corresponding bits are cleared to 0. When they are set to 1, the number of wait states is 2 plus the WAIT signal value. For the external memory space of areas 0, 2, and 6, read cycles are completed in one state plus the number of long wait states (set in wait state controller 3 (WCR3)) when the corresponding bits are cleared to 0. When they are set to 1, the number of wait states is 1 plus the long wait state; when the WAIT signal is at low level as well, a wait state is inserted. The DRAM space (area 1) finishes the column address output cycle in one state (short pitch) when the RW1 bit is 0, and in 2 states plus the WAIT signal value (long pitch) when RW1 is 1. When RW1 is set to 1, the number of wait states selected in wait state insertion bits 1 and 0 (RLW0 and RLW1) for CAS-before-RAS (CBR) refresh of the refresh control register (RCR) are inserted during the CBR refresh cycle, regardless of the status of the WAIT signal. The read cycle of the address/data multiplexed I/O space (area 6) is 4 states plus the wait states from the WAIT signal, regardless of the setting of the RW6 bit. The read cycle of the on-chip peripheral module space (area 5) finishes in 3 states, regardless of the setting of the RW5 bit, and the WAIT signal is not sampled. The read cycles of on-chip ROM (area 0) and on-chip RAM (area 7) finish in 1 state, regardless of the settings of bits RW0 and RW7. The WAIT signal is not sampled for either. Table 8.3 summarizes read cycle state information.
RENESAS 99
Table 8.3
Read Cycle State Description
Read Cycle States External Memory Space Internal space MultiPlexed I/O On-chip Peripheral Module On-chip ROM and RAM 1 state, fixed
WAIT Bits 15-8: Pin Input External Memory RW7-RW0 Signal Space 0 Not sampled during read cycle*1 Sampled during read cycle (initial value) * Areas 1, 3-5,7: 1 state, fixed
DRAM Space
Column address cycle: 1 Areas 0, 2, 6: 1 state state, fixed (short pitch) + long wait state Column address cycle: 2 states + wait Areas 0, 2, 6: 1 state state from WAIT (long + long wait state + pitch)*2 wait state from WAIT Areas 1, 3-5, 7: 2 states + wait states from WAIT
4 states 3 states, fixed + wait states from WAIT
1
Notes: 1. Sampled in the address/data multiplexed I/O space 2. During a CBR refresh, the WAIT signal is ignored and the wait state from the RLW1 and RLW0 bits of RCR is inserted.
* *
Bits 7-2 (reserved): These bits always read as 1. The write value should always be 1. Bit 1 (wait state control during write (WW1)): WW1 determines the number of states in write cycles for the DRAM space (area 1) and whether or not to sample the WAIT signal. When the DRAM enable bit (DRAME) of the BCR is set to 1 and area 1 is being used as DRAM space, clearing WW1 to 0 makes the column address output cycle finish in 1 states (short pitch). When WW1 is set to 1, it finishes in 2 states plus the wait states from the WAIT signal (long pitch).
Note: Write 0 to WW1 only when area 1 is used as DRAM space (DRAME bit of BCR is 1). Never write 0 to WW1 when area 1 is used as external memory space (DRAME is 0).
Bit 1: WW1 0 1 DRAM Space (DRAME = 1) Column address cycle: 1 state (short pitch) Column address cycle: 2 states + wait state from WAIT (long pitch) (initial value) Area 1's External Memory Space (DRAME = 0) Setting inhibited 2 states + wait state from WAIT
*
Bit 0 (reserved): This bit always reads 1. The write value should always be 1.
100 RENESAS
8.2.3
Wait State Control Register 2 (WCR2)
Wait state control register 2 is a 16-bit read/write register that controls the number of states for accessing each area with a DMA single address mode transfer and whether wait states are used. WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or by the standby mode.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 DRW7 1 R/W 7 DWW7 1 R/W 14 DRW6 1 R/W 6 DWW6 1 R/W 13 DRW5 1 R/W 5 DWW5 1 R/W 12 DRW4 1 R/W 4 DWW4 1 R/W 11 DRW3 1 R/W 3 DWW3 1 R/W 10 DRW2 1 R/W 2 DWW2 1 R/W 9 DRW1 1 R/W 1 DWW1 1 R/W 8 DRW0 1 R/W 0 DWW0 1 R/W
*
Bits 15-8 (wait state control during single-mode DMA transfer (DRW7-DRW0)): DRW7- DRW0 determine the number of states in single-mode DMA memory read cycles for each area and whether or not to sample the WAIT signal. Bits DRW7-DRW0 correspond to areas 7-0, respectively. If a bit is cleared to 0, the WAIT signal is not sampled during the single-mode DMA memory read cycle for the corresponding area. If it is set to 1, sampling takes place. For the external memory spaces of areas 1, 3-5, and 7, single-mode DMA memory read cycles are completed in one state when the corresponding bits are cleared to 0. When they are set to 1, the number of wait states is 2 plus the wait states from the WAIT signal. For the external memory space of areas 0, 2, and 6, single-mode DMA memory read cycles are completed in one state plus the long wait state number (set in wait state controller 3 (WCR3)) when the corresponding bits are cleared to 0. When they are set to 1, the number of wait states is 1 plus the long wait state; when the WAIT signal is at low level as well, a wait state is inserted. The DRAM space (area 1) finishes the column address output cycle in one state (short pitch) when the DRW1 bit is 0, and in 2 states plus the wait states from the WAIT signal (long pitch) when DRW1 is 1. The single-mode DMA memory read cycle of the address/data multiplexed I/O space (area 6) is 4 states plus the wait states from the WAIT signal, regardless of the setting of the DRW6 bit. Table 8.4 summarizes single-mode DMA memory read cycle state information.
RENESAS 101
Table 8.4
Single-Mode DMA Memory Read Cycle States (External Memory Space) Description
Single-Mode DMA Memory Read Cycle States (External Memory Space)
Bits 15-8: DRW7-DRW0 0
WAIT Pin Input Signal Not sampled during single-mode DMA memory read cycle*
External Memory Space Areas 1, 3-5,7: 1 state, fixed Areas 0, 2, 6: 1 state + long wait state Areas 1, 3-5, 7: 2 states + wait states from WAIT Areas 0, 2, 6: 1 state + long wait state + Wait state from WAIT
DRAM Space Column address cycle: 1 state, fixed (short pitch) Column address cycle: 2 states + wait state from WAIT (long pitch)
Multiplexed I/O 4 states + wait states from WAIT
1
Sampled during single-mode DMA memory read cycle (initial value)
Note: Sampled in the address/data multiplexed I/O space.
*
Bits 7-0 (single-mode DMA memory write wait state control (DWW7-DWW0)): DWW7- DWW0 determine the number of states in single-mode DMA memory write cycles for each area and whether or not to sample the WAIT signal. Bits DWW7-DWW0 correspond to areas 7-0, respectively. If a bit is cleared to 0, the WAIT signal is not sampled during the singlemode DMA memory write cycle for the corresponding area. If it is set to 1, sampling takes place. The number of states for areas accesses based on bit settings are the same as indicated for single-mode DMA memory read cycles. See bits 15-8, wait state control during single-mode DMA memory transfer (DRW7-DRW0), for details. Table 8.5 summarizes single-mode DMA memory write cycle state information.
102 RENESAS
Table 8.5
Single-Mode DMA Memory Write Cycle States (External Memory Space) Description
Single-mode DMA Memory Write Cycle States (External Memory Space)
Bits 15-8: DWW7-DWW0 0
WAIT Pin Input Signal
External Memory Space
DRAM Space Column address cycle: 1 state, fixed (short pitch) Column address cycle: 2 states + wait state from WAIT (long pitch)
Multiplexed I/O 4 states + wait state from WAIT
Not sampled during Areas 1, 3-5,7: 1 state, fixed single-mode DMA memory write cycle* Areas 0, 2, 6: 1 state + long wait state Sampled during single-mode DMA memory write cycle (initial value) Areas 1, 3-5, 7: 2 states + wait state from WAIT Areas 0, 2, 6: 1 state + long wait state + wait state from WAIT
1
Note: Sampled in the address/data multiplexed I/O space.
8.2.4
Wait State Control Register 3 (WCR3)
Wait state control register 3 is a 16-bit read/write register that controls WAIT pin pull-up and the insertion of long wait states. WCR3 is initialized to H'F800 by a power-on reset. It is not initialized by a manual reset or by the standby mode.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 WPU 1 R/W 7 -- 0 -- 14 13 12 11 A6LW0 1 R/W 3 -- 0 -- 10 -- 0 -- 2 -- 0 -- 9 -- 0 -- 1 -- 0 -- 8 -- 0 -- 0 -- 0 --
A02LW1 A02LW0 A6LW1 1 R/W 6 -- 0 -- 1 R/W 5 -- 0 -- 1 R/W 4 -- 0 --
*
Bit 15 (wait pin pull-up control (WPU)): WPU controls whether the WAIT pin is pulled up or not. When cleared to 0, the pin is not pulled up; when set to 1, it is pulled up.
RENESAS 103
Bit 15: WPU 0 1
Description WAIT pin is not pulled up WAIT pin is pulled up (initial value)
*
Bits 14 and 13 (long wait insertion in areas 0 and 2, bits 1, 0 (A02LW1 and A02LW0)): A02LW1 and A02LW0 select the long wait states to be inserted (1-4 states) when accessing external memory space of areas 0 and 2.
Bit 14: A02LW1 Bit 13: A02LW0 Description 0 0 1 1 0 1 Inserts 1 state Inserts 2 states Inserts 3 states Inserts 4 states (initial value)
*
Bits 12 and 11 (long wait insertion in area 6, bits 1, 0 (A6LW1 and A6LW0)): A6LW1 and A6LW0 select the long wait states to be inserted (1-4 states) when accessing external memory space of area 6.
Bit 11: A6LW0 0 1 Description Inserts 1 state Inserts 2 states Inserts 3 states Inserts 4 states (initial value)
Bit 12: A6LW1 0
1
0 1
*
Bits 10-0 (reserved): These bits always read as 0. The write value should always be 0. DRAM Area Control Register (DCR)
8.2.5
The DRAM area control register (DCR) is a 16-bit read/write register that selects the type of DRAM control signal, the number of precharge cycles, the burst operation mode and the use of address multiplexing. DCR settings are valid only when the DRAME bit of BCR is set to 1. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or by the standby mode.
104 RENESAS
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W:
15 CW2 0 R/W 7 -- 0 --
14 RASD 0 R/W 6 -- 0 --
13 TPC 0 R/W 5 -- 0 --
12 BE 0 R/W 4 -- 0 --
11 CDTY 0 R/W 3 -- 0 --
10 MXE 0 R/W 2 -- 0 --
9 MXC1 0 R/W 1 -- 0 --
8 MXC0 0 R/W 0 -- 0 --
*
Bit 15 (dual-CAS or dual-WE select bit (CW2)): When accessing a 16-bit bus width space, CW2 selects the dual-CAS or the dual-WE method. When cleared to 0, the CASH, CASL, and WRL signals are valid ; when set to 1, the CASL, WRH, and WRL signals are valid. When accessing an 8-bit space, only CASL and WRL signals are valid, regardless of CW2 settings.
Description Dual-CAS: CASH, CASL, and WRL signals are valid (initial value) Dual-WE: CASL, WRH, and WRL signals are valid
Bit 15L: CW2 0 1
*
Bit 14 (RAS down (RASD)): When DRAM access pauses, RASD determines whether to keep RAS low while waiting for the next DRAM access (RAS down mode) or return it to high (RAS up mode). When cleared to 0, the RAS signal returns to high; when set to 1, it stays at low.
Description RAS up mode: Return RAS signal to high and wait for the next DRAM access (initial value) RAS down mode: Keep RAS signal low and wait for the next DRAM access
Bit 14: RASD 0 1
*
Bit 13 (RAS precharge cycle count (TPC)): TPC selects whether the RAS signal precharge cycle (TP) will be 1 state or 2. When TPC is cleared to 0, a 1-state precharge cycle is inserted; when 1 is set, a 2-state precharge cycle is inserted.
Description Inserts 1-state precharge cycle (initial value) Inserts 2-state precharge cycle
Bit 13: TPC 0 1
RENESAS 105
*
Bit 12 (burst operation enable (BE)): BE selects whether or not to perform burst operation, a high speed page mode. When burst operation is not selected (0), the row address is not compared but instead is transferred to the DRAM every time and full access is performed. When burst operation is selected (1), row addresses are compared and burst operation with the same row address as the previous is performed (in this access, no row address is output and the column address and CAS signal alone are output).
Description Normal mode: full access (initial value) Burst operation: high-speed page mode
Bit 12: BE 0 1
*
Bit 11 (CAS duty (CDTY)): CDTY selects 35% or 50% of the TC state as the high-level duty ratio of the signal CAS in the short-pitch access. When cleared to 0, the CAS signal high level duty is 50%; when set to 1, it is 35%. Only set to 1 when the operating frequency is a minimum of 10 MHz.
Description CAS signal high level duty cycle is 50% of the T C state (initial value) CAS signal high level duty cycle is 35% of the T C state
Bit 11: CDTY 0 1
*
Bit 10 (multiplex enable bit (MXE)): MXE determines whether or not DRAM row and column addresses are multiplexed. When cleared to 0, addresses are not multiplexed; when set to 1, they are multiplexed.
Description Multiplex of row and column addresses disabled (initial value) Multiplex of row and column addresses enabled
Bit 10: MXE 0 1
*
Bits 9 and 8 (multiplex shift count 1 and 0 (MXC1 and MXC0)): Shift row addresses downward by a certain number of bits (8-10) when row and column addresses are multiplexed (MXE = 1). Regardless of the MXE bit setting, these bits also select the range of row addresses compared in burst operation.
106 RENESAS
Bit 9: MXC1 0
Bit 8: MXC0 0 1
Row Address Shift (MXE = 1) 8 bits (initial value) 9 bits 10 bits Reserved
Row Address Bits Compared (in burst operation) (MXE = 0 or 1) A8-A27 (initial value) A9-A27 A10-A27 Reserved
1
0 1
Bits 7-0 (reserved): These bits always read as 0. The write value should always be 0. 8.2.6 Refresh Control Register (RCR)
The refresh control register (RCR) is a 16-bit read/write register that controls the start of refreshing and selects the refresh mode and the number of wait states during refresh. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or by the standby mode. To prevent RCR from being written incorrectly, it must be written by a different method from most other registers. A word transfer operation is used, H'5A is written in the top byte, and the actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 -- 0 -- 7 14 -- 0 -- 6 13 -- 0 -- 5 RLW1 0 R/W 12 -- 0 -- 4 RLW0 0 R/W 11 -- 0 -- 3 -- 0 -- 10 -- 0 -- 2 -- 0 -- 9 -- 0 -- 1 -- 0 -- 8 -- 0 -- 0 -- 0 --
RFSHE RMODE 0 R/W 0 R/W
* *
Bit 15-8 (reserved): These bits always read as 0. Bit 7 (refresh control (RFSHE)): RFSHE determines whether or not to perform DRAM refresh operations. When this bit is cleared to 0, no DRAM refresh control is performed and the refresh timer counter (RTCNT) can be used as an 8-bit interval timer. When set to 1, DRAM refresh control is performed.
RENESAS 107
Bit 7: RFSHE 0 1
Description Refresh control disabled. RTCNT can be used as an 8-bit interval timer. (initial value) Refresh control enabled
*
Bit 6 (refresh mode (RMODE)): When DRAM refresh control is selected (RFSHE = 1), RMODE selects whether to perform CAS-before-RAS (CBR) refresh or self-refresh. When this bit is cleared to 0, a CBR refresh is performed at the cycle set in the refresh timer control/status register (RTCSR) and refresh time constant register (RTCOR). When set to 1, it the DRAM does a self-refresh. When refresh control is not selected (RFSHE = 0), the RMODE bit setting is not valid. When canceling self-refresh, set RMODE to 0 with RFSHE set to 1.
Description CAS-before-RAS refresh (initial value) Self-refresh
Bit 6: RMODE 0 1
*
Bits 5 and 4--Insert wait states during CBR refresh bits 1 and 0 (RLW1, RLW0): These bits select the number of wait states to be inserted (1-4) during CAS-before-RAS refresh. When CBR refresh is performed and the RW1 bit of WCR1 is set to 1, the number of wait states selected in the RLW1 and RLW0 is inserted regardless of the WAIT signal. When the RW1 bit is cleared to 0, the RLW1 and RLW0 bit settings are ignored and no wait states are inserted.
Bit 4: RLW0 0 1 Description Inserts 1 state (initial value) Inserts 2 states Inserts 3 states Inserts 4 states
Bit 5: RLW1 0
1
0 1
*
Bits 3-0 (reserved): These bits always read as 0. The write value should always be 0. Refresh Timer Control/Status Register (RTCSR)
8.2.7
The refresh timer control/status register (RTCSR) is a 16-bit read/write register that selects the clock input to refresh timer counter (RTCNT) and controls compare match interrupts (CMI). It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or by the standby mode. To prevent RTCSR from being written incorrectly, it must be written by a different method from most other registers. A word transfer operation is used, H'A5 is written in the top byte and the actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access.
108 RENESAS
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W:
15 -- 0 -- 7 CMF 0 R/W
14 -- 0 -- 6 CMIE 0 R/W
13 -- 0 -- 5 CKS2 0 R/W
12 -- 0 -- 4 CKS1 0 R/W
11 -- 0 -- 3 CKS0 0 R/W
10 -- 0 -- 2 -- 0 --
9 -- 0 -- 1 -- 0 --
8 -- 0 -- 0 -- 0 --
* *
Bits 15-8 (reserved): These bits always read as 0. Bit 7 (compare match flag (CMF)): CMF is a flag that indicates whether the values of RTCNT and the refresh time constant register (RTCOR) match. When 0, the value of RTCNT and RTCOR do not match; when 1, the value of RTCNT and RTCOR match.
Description RTCNT does not equal the value of RTCOR (initial value) To clear CMF, the CPU must read CMF after it has been set to 1, then write a 0 in this bit
Bit 7: CMF 0
1
Value RTCNT is equal to the value of RTCOR
*
Bit 6 (compare match interrupt enable (CMIE)): CMIE enables or disables the compare match interrupt (CMI) generated when CMF is set to 1 in RTCSR (RTCNT value = RTCOR value). When cleared to 0, CMI interrupt is disabled; when set to 1, it is enabled.
Description Compare match interrupt request (CMI) is disabled (initial value) Compare match interrupt request (CMI) is enabled
Bit 6: CMIE 0 1
*
Bits 5-3 (clock select bits 2-0 (CKS2-CKS0)): CKS2-CKS0 select the clock input to RTCNT from among the seven types of clocks created by dividing the system clock (). When the input clock is selected with the CKS2-CKS0 bits, RTCNT starts to increment.
RENESAS 109
Bit 5: CKS2 0
Bit 4: CKS1 0
Bit 3: CKS0 0 1
Description Clock input disabled (initial value) /2 /8 /32 /128 /512 /2048 /4096
1
0 1
1
0
0 1
1
0 1
*
Bits 2-0 (reserved): These bits always read as 0. The write value should always be 0. Refresh Timer Counter (RTCNT)
8.2.8
The refresh timer counter (RTCNT) is a 16-bit read/write register that is used as an 8-bit upcounter that generates the refresh or interrupt request. When the input clock is selected by clock select bits 2-0 (CKS2-CKS0) in RTCSR, that clock makes the RTCNT start incrementing. When the values of RTCNT and the refresh time constant register (RTCOR) match, RTCNT is cleared to H'0000 and the CMF flag of the RTCSR is set to 1. When the RFSHE bit of the RCR is also set to 1, a CAS-before-RAS refresh is performed. When the CMIE bit of the RTCSR is also set to 1, a compare match interrupt (CMI) is generated. Bits 15-8 are reserved bits and do not count. These bits always read as 0. RTCNT is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or by the standby mode. To prevent RTCSR from being written incorrectly, it must be written by a different method from most other registers. A word transfer operation is used, H'69 is written in the top byte and the actual data is written in the lower byte. For details, see section 8.2.11, Register Access.
110 RENESAS
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W:
15 -- 0 -- 7
14 -- 0 -- 6
13 -- 0 -- 5
12 -- 0 -- 4
11 -- 0 -- 3
10 -- 0 -- 2
9 -- 0 -- 1
8 -- 0 -- 0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
RENESAS 111
8.2.9
Refresh Time Constant Register (RTCOR)
The refresh time constant register (RTCOR) is a 16-bit read/write register that sets the compare match cycle used with RTCNT. The values in RTCOR and RTCNT are constantly compared. When they match, the compare-match flag (CMF) is set in RTCNT and RTCSR is cleared to H'0000. If the bit RFSHE in RCR is set to 1 when this happens, a CAS before RAS (CBR) refresh is performed. When the CMIE bit of the RTCSR is also set to 1, a compare match interrupt (CMI) is generated. Bits 15-8 are reserved bits and cannot be used to set the cycle. These bits always read as 0. RTCOR is initialized to H'00FF by a power-on reset, but is not initialized by a manual reset or by the standby mode. To prevent RTCOR from being written incorrectly, it must be written by a different method from most other registers. A word transfer operation is used, H'96 is written in the top byte and the actual data is written in the lower byte. For details, see section 8.2.11, Note on Register Access.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 15 -- 0 -- 7 14 -- 0 -- 6 13 -- 0 -- 5 12 -- 0 -- 4 11 -- 0 -- 3 10 -- 0 -- 2 9 -- 0 -- 1 8 -- 0 -- 0
8.2.10
Parity Control Register (PCR)
The parity control register (PCR) is a 16-bit read/write register that selects the parity polarity and space to be parity checked. PCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or by the standby mode.
112 RENESAS
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W:
15 PEF 0 R/W 7 -- 0 --
14 PFRC 0 R/W 6 -- 0 --
13 PEO 0 R/W 5 -- 0 --
12
11
10 -- 0 -- 2 -- 0 --
9 -- 0 -- 1 -- 0 --
8 -- 0 -- 0 -- 0 --
PCHK1 PCHK0 0 R/W 4 -- 0 -- 0 R/W 3 -- 0 --
*
Bit 15 (parity error flag (PEF)): When a parity check is done, PEF indicates whether a parity error has occurred. 0 indicates that no parity error has occurred; 1 indicates that a parity error has occurred.
Description No parity error (initial value). Cleared by reading PEF after it has been set to 1, then writing 0 in PEF.
Bit 15: PEF 0
1
Parity error has occurred.
*
Bit 14 (parity output force (PFRC)): PFRC selects whether to produce a forced parity output for testing the parity error check function. When cleared to 0, there is no forced output; when set to 1, it produces a forced output of high level from the DPH and DPL pins when data is output, regardless of the parity.
Description Parity output not forced (initial value) High output forced
Bit 14: PFRC 0 1
*
Bit 13 (parity polarity (PEO)): PEO selects even or odd parity. When cleared to 0, parity is even; when set to 1, parity is odd.
Description Even parity (initial value) Odd parity
Bit 13: PEO 0 1
*
Bits 12 and 11 (parity check enable bits 1, 0 (PCHK1 and PCHK0)): These bits determine whether or not a parity is checked and generated, and select the check and generation spaces.
RENESAS 113
Bit 12: PCHK1 0
Bit 11: PCHK0 0 1
Description Parity not checked and not generated (initial value) Parity checked and generated only in DRAM area Parity checked and generated in DRAM area and area 2 Reserved
1
0 1
*
Bits 10-0 (reserved): These bits always read as 0. The write value should always be 0. Notes on Register Access
8.2.11
RCR, RTCSR, RTCNT, and RTCOR differ from other registers in being more difficult to write. Data requires a password when it is written. This prevents data from being mistakenly overwritten by program overruns and the like. Writing to RCR, RTCSR, RTCNT, and RTCOR: Use only word transfer instructions. You cannot write with byte transfer instructions. As figure 8.2 shows, when writing to RCR, place H'5A in the upper byte and the write data in the lower byte. When writing to RTCSR, place H'A5 in the upper byte and the write data in the lower byte. When writing to RTCNT, place H'69 in the upper byte and the write data in the lower byte. When writing to RTCOR, place H'96 in the upper byte and the write data in the lower byte. These transfers write data in the lower byte to the respective registers. If the upper byte differs from the above passwords, no writing occurs.
15 RCR 15 RTCSR 15 RTCNT 15 RTCOR H'96 H'69 H'A5 H'5A
87 Write data 87 Write data 87 Write data 87 Write data
0
0
0
0
Figure 8.2 Writing to RCR, RTCSR, RTCNT, and RTCOR Reading from RCR, RTCSR, RTCNT, and RTCORP: These registers are read like other registers. They can be read by byte and word transfer instructions. If read by word transfer, the value of the upper eight bits is H'00.
114 RENESAS
8.3
8.3.1
Address Space Subdivision
Address Spaces and Areas
Figure 8.3 shows the address format used in this LSI.
4 Gbyte space 128 Mbyte space 16 Mbyte space 4 Mbyte space A31-A28 A27 A26-A24 A23,A22 A21 Output address: Output from address pins A21-A0 Ignore: Only valid when the address multiplex function is being used in the DRAM space (area 1); not output in other cases. When not output, becomes shadow. Area selection: Decoded to become chip select signals CS0-CS7 for areas 0-7 Basic bus width selection: Not output externally, but used for basic bus width selection When 0, (H'0000000-H'7FFFFFF), the basic bus width is 8 bits. When 1, (H'8000000-H'FFFFFFF) the basic bus width is 16 bits. Ignore: Always ignore, not output externally A0
Figure 8.3 Address Format Since this LSI uses a 32-bit address, 4 Gbytes of space can be accessed on the architecture; however, the upper 4 bits (A31-A28) are always ignored and not output. Bit A27 is basically only used for switching the bus width. When the A27 bit is 0 (H'0000000-H'7FFFFFF), the bus width is 8 bits; when the A27 bit is 1 (H'8000000-H'FFFFFFF), the bus width is 16 bits. Of the remaining 27 bits (A26-A0), a total 128 Mbyte can thus be accessed. The 128 Mbyte space is subdivided into 8 areas (areas 0-7) of 16 Mbytes each according to the values of bits A26-A24. The space with bits A26-A24 as 000 is area 0 and the space 111 is area 7. The A26-A24 bits are decoded and become the chip select signals (CS0-CS7) of the corresponding areas 0-7 and output. Table 8.6 shows how the space is divided.
RENESAS 115
Table 8.6
How Space is Divided
Assign-able Memory Capacity (linear space) 16 kB* 3 32 kB* 4 4 MB 4 MB 16 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 16 32 kB* 3 kB* 4 8 32 8/16*5 16 16 16 16 16 16 16 32 CS7 -- CS0 CS1 RAS CAS CS2 CS3 CS4 CS5 CS6 -- Bus Width 32 8/16*5 8 8 8 8 8 8/16*7 8/16*8 CS Output -- CS0 CS1 RAS CAS CS2 CS3 CS4 -- CS6
Area Address 0
H'0000000 - H'0FFFFFF On-chip ROM*1 External memory*2
1 2 3 4 5 6 7 0
H'1000000 - H'1FFFFFF External memory DRAM*6 H'2000000 - H'2FFFFFF External memory H'3000000 - H'3FFFFFF External memory H'4000000 - H'4FFFFFF External memory H'6000000 - H'6FFFFFF External memory*9 Multiplexed I/O H'7000000 - H'7FFFFFF External memory H'8000000 - H'8FFFFFF On-chip ROM*1
H'5000000 - H'5FFFFFF On-chip peripheral module 512 B
External memory*2 1 2 3 4 5 6 7 H'9000000 - H'9FFFFFF External memory DRAM*6 H'A000000 - H'AFFFFFF External memory H'B000000 - H'BFFFFFF External memory H'C000000 - H'CFFFFFF External memory H'D000000 - H'DFFFFFF External memory H'E000000 - H'EFFFFFF External memory H'F000000 - H'FFFFFFF On-chip RAM
4 MB 4 MB 16 MB 4 MB 4 MB 4 MB 4 MB 4 MB 1 kB
Notes: 1. 2. 3. 4. 5. 6. 7.
When MD2-MD0 pins are 010 When MD2-MD0 pins are 000 or 001 For SH7020 For SH7021 Select with MD0 pin Select with DRAME bit in BCR Divided into 8-bit and 16-bit space according to value of address bit A8 (Long word accesses are inhibited, however, in on-chip peripheral modules with bus widths of 8 bits. Some on-chip peripheral modules with bus widths of 16 bits also have registers that are only byte-accessible and registers for which byte access is inhibited. For details, see the sections on the individual modules.) 8. Divided into 8-bit space and 16-bit space by value of address bit A14 9. Select with IOE bit of BCR
116 RENESAS
As figure 8.4 shows, specific spaces such as DRAM space and address/data multiplexed I/O space are allocated to the 8 areas. Each of the spaces is equipped with the necessary interfaces. The control signals needed by DRAM and peripheral LSIs will be output by the chip to devices connected to an area allocated to the appropriate type of space. 8.3.2 Bus Width
The primary bus width selection on for this chip is made by switching between 8-bit and 16 bit using the A27 bit. When A27 is 0, the bus width is 8 bits and data is input/output through the AD7-AD0 pins; when A27 is 1, the size is 16 bits and data is input/output through the AD15- AD0 pins for word accesses. For byte access, the top byte is input/output through AD15-AD8 and the lower byte through AD7-AD0. When the bus width is 8 bits or byte access is being performed with a 16-bit bus width, the status of the eight AD pins that are not inputting/outputting data is as shown in appendix B, Pin States. Bus widths are also determined by conditions other than the A27 bit for specific areas: * Area 0 is an 8-bit external memory space when the MD2-MD0 pins are 000, a 16-bit external memory space when the same bits are 001, and a 32-bit on-chip ROM space when they are 010. Area 5 is an 8-bit on-chip peripheral module space when the A27 bit and A8 bit are both 0 and a 16-bit on-chip peripheral module space when the A27 bit is 0 and the A8 bit is 1. When the A27 bit is 1, it is a 16-bit external memory space. Area 6 is an 8-bit bus width when the A27 bit and A14 bit are both 0 and a 16-bit bus width when the A27 bit is 0 and the A14 bit is 1. When the A27 bit is 1, it is a 16-bit space. Area 7 is a 32-bit on-chip RAM space when the A27 bit is 1 and an 8-bit external memory space when the A27 bit is 0.
*
* *
Word (16-bit) data accessed from 8-bit bus areas and longword (32-bit) data accessed from 16-bit bus areas require two consecutive accesses. Longword (32-bit) data accessed from 8-bit bus areas requires four consecutive accesses. 8.3.3 Chip Select Signals (CS0-CS7)
When the A26-A24 bits of the address are decoded, they become chip select signals (CS0-CS7) for areas 0-7. When an area is accessed, the corresponding chip select pins are driven low. Table 8.7 shows the relationship between the A26-A24 bits and the chip select signals.
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Table 8.7
A26-A24 Bits and Chip Select Signals
Address
A26 0
A25 0
A24 0 1
Area Selected Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7
Chip Select Pin Driven Low CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7
1
0 1
1
0
0 1
1
0 1
The chip select signal is output only for external accesses. When accessing the on-chip ROM (area 0), on-chip peripheral modules (area 5) and on-chip RAM (area 7), the CS0, CS5, and CS7 pins are not driven low. When accessing DRAM space (area 1), select the RAS and CAS signals with the pin function controller. 8.3.4 Shadows
The size of each area is 16 Mbytes, which can be specified with 24 address bits A23-A0 for 8-bit spaces and 16-bit spaces alike. Bits A23 and A22, however, output externally only when the address multiplex function is used in DRAM space (area 1); in all other cases, there is no output, so the actually accessible area for all areas is the 4 Mbyte that can be specified with 22 bits A21- A0. No matter what the values of A23 and A22, the same 4 Mbytes of actual space is accessed. As illustrated in figure 8.4 (a), the A23 and A22 bit regions 00, 01, 10 and 11 are called shadows of actual areas. Shadows are allocated in 4-Mbyte units for both 8-bit and 16-bit bus widths. When the same addresses H'3200000, H'3600000, H'3A00000 and H'3E00000 are specified for values A21-A0, as shown in figure 8.4 (b), the same actual space is accessed regardless of the A23 and A22 bits. In areas whose bus widths are switchable using the A27 address bit, the shadow of the same actual space is allocated to both A27 = 0 spaces and A27 = 1 spaces (figure 8.4(a)). When the value of A27 is changed, the valid AD pins switch from AD15-AD0 to AD7-AD0, but the actual space accessed remains the same. The spaces of on-chip ROM (area 0), DRAM (area 1), on-chip peripheral modules (area 5) and onchip RAM (area 7) have shadows of different sizes from those discussed above. See section 8.3.5, Description of Areas, for details.
118 RENESAS
Logical address space
H'B000000 H'3000000 H'B3FFFFF H'B400000 H'33FFFFF H'3400000 H'B7FFFFF H'B800000 H'37FFFFF H'BBFFFFF H'BC00000 H'BFFFFFF H'3800000 H'3BFFFFF H'3C00000 H'3FFFFFF 16-bit space
Shadow (A23, A22 = 00) Shadow (A23, A22 = 01) Shadow (A23, A22 = 10) Shadow (A23, A22 = 11) 8-bit space a. Shadow allocation Actual space Area accessible with A21-A0 4 Mbytes
Logical address space
H'3000000 H'3200000 H'33FFFFF H'3400000 H'3600000 H'37FFFFF H'3800000 H'3A00000 H'3BFFFFF H'3C00000 H'3E00000 H'3FFFFFF
Location indicated by address Actual space Location indicated by address Location actually accessed Location indicated by address
Location indicated by address 8-bit space
b. Actual space accessed when addresses are specified
Figure 8.4 Shadows
RENESAS 119
8.3.5
Area Description
Area 0: Area 0 is the area where addresses A26-A24 are 000 and its address range is H'0000000- H'0FFFFFF and H'8000000-H'8FFFFFF. Figure 8.5 is a memory map of area 0. Area 0 can be set for use as on-chip ROM space or external memory space with the mode pins (MD2-MD0). The MD2-MD0 pins also determine the bus width, regardless of the A27 address bit. When MD2-MD0 are 000, area 0 is an 8-bit external memory space; when they are 001, area 0 is a 16-bit external memory space; and when they are 010, it is a 32-bit on-chip ROM space. In the SH7020, the capacity of the on-chip ROM is 16 kbyte, so bits A23-A14 are ignored in onchip ROM space and the shadow is in 16 kbyte units. In the SH7021, the capacity of the on-chip ROM is 32 kbyte, so bits A23-A15 are ignored in on-chip ROM space and the shadow is in 32 kbyte units. The CSO signal is disabled in on-chip ROM space. In external memory space, the A23 and A22 bits are not output and the shadow is in 4-Mbyte units. When external memory space is accessed, the CS0 signal is valid. The external memory space has a long wait function, so between 1 and 4 states can be selected for the number of long waits inserted into the bus cycle using the areas 0 and 2 long wait insertion bits (A02LW1, A02LW0) of wait state controller 3 (WCR3).
120 RENESAS
Logical address space
H'8000000 H'8003FFF(SH7020) H'8007FFF(SH7021) H'0000000 H'8004000(SH7020) H'0003FFF (SH7020) H'8008000(SH7021) H'0007FFF (SH7021)
H'004000 (SH7020) H'0008000 (SH7021) H'8000000
Logical address space
Shadow Shadow Shadow
H'83FFFFF H'8400000
H'0000000
Shadow
H'03FFFFF H'0400000
H'8FFC000 (SH7020) H'8FF8000 (SH7021) H'0FFC000 (SH7020) H'0FF8000 (SH7021) H'0FFFFFF
Shadow Shadow Shadow
Actual space H'07FFFFF On-chip ROM H'0800000 SH7020: 16 kbyte SH7021: H'8BFFFFF 32 kbyte H'8C00000 * Valid H'0BFFFFF addresses H'0C00000 A15-A0 (A23-A16 H'8FFFFFF ignored) * CS0 not valid H'0FFFFFF 8 or 16 bit space
H'87FFFFF H'8800000
Shadow
Actual space External memory space (4 Mbytes)
Shadow * MD2-MD0 = 000: 8-bit access, 001: 16-bit access * Valid addresses A21-A0 (A23 and A22 not output) * CS0 valid * Long wait function
Shadow
8 or 16 bit space
32-bit space 32-bit space
MD2-MD0 = 010
MD2-MD0 = 000 or 001
Note: The bus width of area 0 is determined by the MD2-MD0 pins regardless of the A27 bit setting.
Figure 85 Memory Map of Area 0 Area 1: Area 1 is the area where addresses A26-A24 are 001 and its address range is H'1000000- H'1FFFFFF and H'9000000-H'9FFFFFF. Figure 8.6 is a memory map of area 1. Area 1 can be set for use as DRAM space or external memory space with the DRAM enable bit (DRAME) of the bus control register (BCR). When the DRAME bit is 0, it is external memory space; when DRAME is 1, it is DRAM space. In external memory space, the bus width is 8 bits when the A27 bit is 0 and 16 bits when it is 1. Bits A23 and A22 are not output and the shadow is in 4-Mbyte units. When external memory is accessed, the CS1 signal is valid. DRAM space is a type of external memory space, but it is configured especially to be connected to DRAM so it outputs strobe signals required for this purpose. Its bus width is 8 bits when it is 0 and 16 bits when it is 1. When the multiplex enable bit (MXE) of the DRAM control register (DCR) is
RENESAS 121
set to 1 to use the address multiplex function, bits A23-A0 are multiplexed and output from pins A15-A0, so a maximum 16-Mbyte space can be used. When DRAM space is accessed, the CS1 signal is not valid and the pin function controller should be set for access with CAS (CASH and CASL) and RAS signals.
Logical address space
H'9000000 H'1000000 H'9000000
Logical address space Actual space
H'1000000
H'93FFFFF H'9400000 H'13FFFFF H'1400000
Shadow
Actual space Shadow External memory space (4 Mbytes) * Valid address A21-A0 (A23 and A22 not output) * CS1 H'9FFFFFF valid
H'1FFFFFF
H'97FFFFF H'9800000 H'17FFFFF H'1800000
Shadow
DRAM space (maximum 16 Mbytes)
H'9BFFFFF H'9C00000 H'1BFFFFF H'1C00000
Shadow
H'9FFFFFF H'1FFFFFF A27 = 1: 16-bit space
Shadow
A27 = 0: 8-bit space
A27 = 1: A27 = 0: 16-bit space 8-bit space
* Multiplexed (MXE = 1): 16-bit space * Not multiplexed (MXE = 0): 4 Mbyte space * CS1 not valid (CAS, RAS output)
DRAME = 0 or DRAME = 1, MXE = 0
DRAME = 1
Figure 8.6 Memory Map of Area 1 Areas 2-4: Areas 2-4 are the areas where addresses A26-A24 are 010, 011 and 100, respectively, and their address ranges are H'2000000-H'2FFFFFF and H'A000000-H'AFFFFFF (area 2), H'3000000-H'3FFFFFF and H'B000000-H'BFFFFFF (area 3), and H'4000000-H'4FFFFFF and H'C000000-H'CFFFFFF (area 4). Figure 8.7 is a memory map of area 2, which is representative of areas 2-4.
122 RENESAS
Areas 2-4 are always used as external memory space. The bus width is 8 bits when the A27 bit is 0 and 16 bits when it is 1. A23 and A22 bits are not output and the shadow is in 4-Mbyte units. When areas 2-4 are accessed, the CS2, CS3, and CS4 signals are valid. Area 2 has a long wait function, so between 1 and 4 states can be selected for the number of long waits inserted into the bus cycle using the bits A02LW1 and A02LW0 of WCR3.
Logical address space
H'A000000 H'2000000
H'A3FFFFF H'A400000 H'23FFFFF H'2400000
Shadow
Actual space
H'A7FFFFF H'A800000 H'27FFFFF H'2800000
Shadow External memory space (4 Mbytes)
H'ABFFFFF H'AC00000 H'2BFFFFF H'2C00000
Shadow
* Valid addresses A21-A0 (A23 and A22 not output) * CS2 valid * Long wait function
H'AFFFFFF H'2FFFFFF 16-bit space
Shadow
8-bit space
Figure 8.7 Memory Map of Area 2
RENESAS 123
Area 5: Area 5 is the area where addresses A26-A24 are 101 and its address range is H'5000000- H'5FFFFFF and H'D000000-H'DFFFFFF. Figure 8.8 is a memory map of area 5. Area 5 is allocated to on-chip peripheral module space when the A27 address bit is 0 and external memory space when A27 is 1. In on-chip peripheral module space, bits A23-A9 are ignored and the shadows are in 512-byte units. The bus width is 8 bits when the A8 bit is 0 and 16 bits when A8 is 1. When on-chip peripheral module space is accessed, the CS5 signal is not valid. In external memory space, the A23 and A22 bits are not output and the shadow is in 4-Mbyte units. The bus width is always 16 bits. When external memory space is accessed, the CS5 signal is valid.
Logical address space H'5000000 H'50001FF Shadow Shadow Shadow
Logical address space H'D000000 Shadow H'D3FFFFF H'D400000 Actual space H'D7FFFFF H'D800000 Shadow Shadow
Actual space External memory space (4 Mbytes)
* Valid addresses A21-A0 A23 and A22 not output) * CS5 valid
On chip peripheral module space (512 bytes)
Shadow Shadow H'5FFFE00 H'5FFFFFF Shadow 8 or 16-bit space
A8 = 0: H'DBFFFFF H'DC00000 8-bit space A8 = 1: 16-bit space* * Ignored Shadow addresses: A23-A9 (Valid addresses H'DFFFFFF 16-bit space A8-A0) * CS5 not valid
Note: Some registers in onchip peripheral modules can only be accessed as 8-bit registers even though they occupy 16 bits (see Appendix A).
Figure 8.8 Memory Map of Area 5 Area 6: Area 6 is the area where addresses A26-A24 are 110 and its address range is H'6000000- H'6FFFFFF and H'E000000-H'EFFFFFF. Figure 8.9 is a memory map of area 6.
124 RENESAS
In area 6, the space when A27 is 0 is allocated to address/data multiplexed I/O space when the multiplexed I/O enable bit (IOE) of the bus control register (BCR) is 1 and external memory space when the IOE bit is 0. When A27 is 1, it is always external memory space. The multiplexed I/O space is a type of external memory space but the address and data are multiplexed and output from AD15-AD0 or AD7-AD0. The bus width is 8 bits when the A14 bit is 0 and 16 bits when the A14 bit is 1. The A23 and A22 bits are not output and the shadow is in 4Mbyte units. When multiplexed I/O space is accessed, the CS6 signal is valid. In external memory space, the bus width is 8 bits when both the A27 and A14 bits are 0 and 16 bits when the A27 bit is 0 and the A14 bit is 1. When the A27 bit is 1, it is always a 16-bit space. The A23 and A22 bits are not output and the shadow is in 4-Mbyte units. When external memory is accessed, the CS6 signal is valid. The external memory space has a long wait function so between 1 and 4 states can be selected for the number of long waits inserted into the bus cycle using the area 6 long wait insertion bits (A6LW1 and A6LW0) of WCR3.
RENESAS 125
Logical address space H'6000000 Shadow
H'63FFFFF H'6400000
Logical address space H'E000000 Shadow Actual space
H'E3FFFFF H'E400000
Actual space Shadow
External memory space (4 Mbytes)
Shadow
H'67FFFFF H'6800000
Multiplexed I/O space or external memory space (4 Mbytes)
H'E7FFFFF H'E800000
Shadow
H'6BFFFFF H'6C00000
Shadow
H'6FFFFFF
8 or 16-bit space
Shadow * Valid * IOE = 1: addresses address/data A21-A0 (A23 multiplexed I/O H'EBFFFFF H'EC00000 and A22 not space; output) IOE = 0: external * CS6 valid memory space Shadow * Long wait * A14 = 0: 8-bit space function A14 = 1: 16-bit space * Valid addresses H'EFFFFFF A21-A0 (A23 and 16-bit space A22 not output) * CS6 valid * Long wait function
Figure 8.9 Memory Map of Area 6 Area 7: Area 7 is the area where addresses A26-A24 are 111 and its address range is H'7000000- H'7FFFFFF and H'F000000-H'FFFFFFF. Figure 8.10 is a memory map of area 7. Area 7 is allocated to external memory space when A27 is 0 and on-chip RAM space when A27 is 1. In external memory space, the bus width is 8 bits. The A23 and A22 bits are not output and the shadow is in 4-Mbyte units. When external memory is accessed, the CS7 signal is valid. The on-chip RAM space has an bus width of 32 bits. The on-chip RAM capacity is 1 kbytes, so A23-A10 are ignored and the shadows are in 8-kbyte units. During on-chip RAM access, the CS7 signal is not valid.
126 RENESAS
Logical address space H'7000000 Shadow H'73FFFFF H'7400000 Shadow H'77FFFFF H'7800000 Shadow H'7BFFFFF H'7C00000 Shadow H'7FFFFFF 8-bit space
Logical address space H'F000000 H'F0003FF Shadow Shadow Shadow Actual space External memory space (4 Mbytes)
* Valid addresses A21-A0 (A23 and A22 not output) * CS7 valid
Actual space
Shadow Shadow H'FFFFC00 H'FFFFFFF Shadow 32-bit space
* On-chip RAM space 1 Kbytes, * Valid addresses A9-A0 (A23-A10 not output) * CS7 not valid
Figure 8 10 Memory Map of Area 7
RENESAS 127
8.4
Accessing External Memory Space
In external memory space, strobe signal is output based on the assumption of a directly connected SRAM. The external memory space is allocated to the following areas: * * * * * * Area 0 (when MD2-MD0 are 000 or 001) Area 1 (when the DRAM enable bit (DRAME) of the BCR is 0) Areas 2-4 Area 5 (space where address A27 is 1) Area 6 (when the multiplexed I/O enable bit (IOE) bit of the BCR is 0, or space where address A27 is 1) Area 7 (space where address A27 is 0) Basic Timing
8.4.1
The bus cycle for external memory space access is 1 or 2 states. The number of states is controlled with the wait states by the settings of wait state control registers 1-3 (WCR1-WCR3). For details, see section 8.4.2., Wait State Control. Figures 8.11 and 8.12 illustrate the basic timing of external memory space access.
T1 CK
A21-A0
CSn
RD (Read) AD15-AD0 (Read)
Figure 8.11 Basic Timing of External Memory Space Access (1-state read timing)
128 RENESAS
T1 CK
T2
A21-A0
CSn
When RDDTY = 0
RD Read AD15-AD0
When RDDTY = 1
WRH, WRL Write AD15-AD0
Figure 8.12 Basic Timing of External Memory Space Access (2-state read timing) High-level duties of 35% and 50% can be selected for the RD signal using the RD duty bit (RDDTY) of the BCR. When RDDTY is set to 1, the high-level duty is 35% of the T1 state, enabling longer access times for external devices. Only set to 1 when the operating frequency is a minimum of 10 MHz. 8.4.2 Wait State Control
The number of external memory space access states and the insertion of wait states can be controlled using the WCR1-WCR3 bits. The bus cycles that can be controlled are the CPU read cycle and the DMAC dual mode read cycle. The bus cycle that can be controlled using the WCR2 is the DMAC single-mode read/write cycle. Table 8.8 shows the number of states and number of wait states in the access cycles to external memory spaces.
RENESAS 129
Table 8.8
Number of States and Number of Wait States in the Access Cycles to External Memory Spaces
CPU read cycle, DMAC dual mode read cycle, DMAC single mode read/write cycle CPU Write Cycle and DMAC Dual Mode Write Cycle (Cannot be controlled by WCR1)*2
Area 1, 3-5, 7 0, 2, 6 (long wait available)
Corresponding Bits in WCR1 and WCR2 = 0
Corresponding Bits in WCR1 and WCR2 = 1
1 cycle fixed; WAIT signal 2 cycles fixed + wait state from WAIT signal ignored 1 cycle + long wait state, WAIT signal ignored 1 cycle + long wait state*1 + wait state from WAIT signal
Notes: 1. The number of long wait states is set by WCR3. 2. When DRAME = 1, short pitch/long pitch is selected with the WW1 bit of the WCR1. 3. Pin wait cannot be used for the CS7 and WAIT pins of area 3 because they are multiplexed.
For the CPU read cycle, DMAC dual mode read cycle and DMAC single mode read/write cycle, the access cycle is completed in 1 state when the corresponding bits of WCR1 and WCR2 for areas 1, 3-5, and 7 are cleared to 0 and the WAIT pin input signal is not sampled. When the bits are set to 1, the WAIT signal is sampled and the number of states is 2 plus the number of wait states in the WAIT signal. The WAIT signal is sampled at the rise of the system clock (CK) directly preceding the second state of the bus cycle and the wait states are inserted as long as the level is low. When a high level is detected, it shifts to the second state (final state). Figure 8.13 shows the wait state timing when accessing the external memory spaces of areas 1, 3, 4, 5, and 7.
130 RENESAS
T1 CK
Tw (wait state)
T2
A21-A0
CSn
RD Read AD15-AD0
WRH, WRL Write AD15-AD0
WAIT
Figure 8.13 Wait State Timing for External Memory Space Access (2 states plus wait states from WAIT signal) Areas 0, 2 and 6 have long wait functions. When the corresponding bits in WCR1 and WCR2 are cleared to 0, the access cycle is 1 state plus the number of long wait states (set in WCR3, selectable between 1 and 4) and the WAIT pin input signal is not sampled. When the bits are set to 1, the WAIT signal is sampled and the number of states is 1 plus the number of long wait states plus the number of wait states in the WAIT signal. The WAIT signal is sampled at the rise of the system clock (CK) directly preceding the last long wait state and the wait states are inserted as long as the level is low. When a high level is detected, it shifts to the final long wait state. Figure 8.14 shows the wait state timing when accessing the external memory spaces of areas 0, 2, and 6.
RENESAS 131
Wait states set in WCR3 T1 CK TLW1 TLW2
Wait state Wait from WAIT states set signal input in WCR3 TW TLW3
A21-A0
CSn
RD Read AD15-AD0
WRH, WRL Write AD15-AD0
WAIT
Figure 8.14 Wait State Timing for External Memory Space Access (1 state plus long wait state (when set to insert 3 states) plus wait states from WAIT signal) For CPU write cycles and DMAC dual mode write cycles to external memory space, the number of states and wait state insertion cannot be controlled by WCR1. In areas 1, 3, 4, 5, and 7, the WAIT signal is sampled and the number of states is 2 plus the number of wait states in the WAIT signal (figure 8.13). In areas 0, 2 and 6, the number of states is 1 state plus the number of long wait states plus the number of wait states in the WAIT signal (figure 8.14). Never write 0 in bits 7-2 and 0 of WCR1; only write 1. When area 1 is being used as external memory space, never write 0 to bit 1 (WW1); always write 1.
132 RENESAS
8.4.3
Byte Access Control
The upper byte and lower byte control signals when 16-bit bus width space is being accessed can be selected from (WRH, WRL, A0) or (WR, HBS, LBS). When the byte access select bit (BAS) of the BCR is set to 1, the WRH, WRL, and A0 pins output WR, LBS and HBS signals. Figure 8.15 illustrates the control signal output timing in the byte write cycle.
Upper byte access T1 T2
Lower byte access T1 T2
CK
A0
BAS = 0
WRH
WRL HBS BAS = 1
LBS WR
Figure 8.15 Byte Access Control Timing For External Memory Space Access (Write Cycle) The WRH, WRL system and the HBS, LBS system are available as byte access signals for the 16bit space in the address/data multiplexing space and the external memory space. These strobe signals are assigned to pins in the manner: A0/HBS, WRH/LBS, WRL/WR, and the BAS bit of the bus control register (BCR) is used to switch specify signal sending. Note that the byte access signals are strobe signals dedicated to byte access to a 16-bit space and not to be used for byte access to an 8-bit space. When making an access to an 8-bit space, use the A0/HBS pin as A0 irrespective of the BAS bit value (0 or 1) to use the WRL/WR pin as the WR pin, and avoid using the WRH/LBS pin.
RENESAS 133
8.5
DRAM Interface Operation
When the DRAM enable bit (DRAME) of the BCR is set to 1, area 1 becomes DRAM space and the DRAM interface function is available, which permits direct connection of this LSI to DRAMs. 8.5.1 DRAM Address Multiplexing
When the multiplex enable bit (MXE) of the DRAM area control register (DCR) is set to 1, row addresses and column addresses are multiplexed. This allows DRAMs that require multiplexing of row and column addresses to be connected directly to the SH microprocessors without additional multiplexing circuits. When addresses are multiplexed (MXE = 1), setting of the DCR's multiplex shift bits (MXC1, MXC0) allows selection of eight, nine and ten-bit row address shifting. Table 8.9 illustrates the relationship between MXC1/MXC0 bits and address multiplexing.
134 RENESAS
Table 8.9
Relationship between Multiplex Shift Count Bits (MXC1, MXC0) and Address Multiplexing
Shift Amount 8 bits Output Row Address Output Column Address A21 A20 Undefined Value A19 A18 A17 A16 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 Undefined Value Shift Amount 9 bits Output Row Address Output Column Address A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Undefined Value Shift Amount 10 bits Output Row Address Output Column Address A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Output Pin A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Notes: The MXC1=1, MX0=1 setting is reserved. Do not use it.
For example, when MXC1 and MXC0 are set to 00 and an 8-bit shift is selected, the A23-A8 address bit values are output to pins A15-A0 as row addresses. The values for A21-A16 are undefined. The values of bits address A21-A0 are output to pins A21-A0 as column addresses. Figure 8.16 depicts address multiplexing with an 8-bit shift.
RENESAS 135
RAS = Low level Internal address A23 A8 A7 A0
Address pin
A21
A16 A15
A0
Undefined output CAS = Low level Internal address A23 A22 A21 A0
Address pin
A21
A0
Figure 8.16 Address Multiplexing States (8-bit shift) 8.5.2 Basic Timing
There are two types of DRAM accesses: short pitch and long pitch. Short pitch or long pitch can be selected for the respective bus cycles using the RW1 and WW1 bits of WCR1 and the DRW1 and DWW1 bits of WCR2. When the corresponding bits are cleared to 0, DRAM access is short pitch and column address output occurs in 1 state. When these bits are 1, DRAM access is long pitch and column address output occurs in 2 states. Figure 8.17 shows short pitch timing; figure 8.18 shows long pitch timing. The high-level duty of the CAS signal can also be selected between 50% and 35% of the T C state when access is short pitch. By setting the CDTY bit to 1, high level duty becomes 35% and DRAM access time can be lengthened. Only set to 1 when the operating frequency is a minimum of 10 MHz.
136 RENESAS
Tp CK
Tr
Tc
A21-A0
Row address
Column address
RAS
CDTY =0
CAS
CDTY =1
WRH, WRL
Read
AD15-AD0
WRH, WRL
Write
AD15-AD0
Figure 8.17 Short Pitch Access Timing
RENESAS 137
Tp CK
Tr
Tc1
Tc2
A21-A0
Row address
Column address
RAS
CAS
WRH, WRL
Read
AD15-AD0
WRH, WRL
Write
AD15-AD0
Figure 8.18 Long Pitch Access Timing 8.5.3 Wait State Control
Precharge State Control: When the microprocessor clock frequency is raised and the cycle period shortened, 1 cycle may not always be sufficient for the precharge time for the RAS signal when the DRAM is accessed. The BSC allows the precharge cycle to be set to 1 state or 2 states using the RAS signal precharge cycles bit (TPC) of the DCR. When the TPC bit is 0, the precharge cycle is 1 state; when TPC is 1, the precharge cycle is 2 states. Figure 8.19 shows the timing when the precharge cycle is 2 states.
138 RENESAS
Tp1
CK
Tp2
Tr
Tc 1
Tc2
A21-A0
Row address
Column address
RAS
CAS
Figure 8.19 Precharge Timing (Long Pitch) Control of Insertion of Wait States Using the WAIT Pin Input Signal: The number of wait states inserted into the DRAM access cycle can be controlled by setting WCR1 and WCR2. When the corresponding bits in WCR1 and WCR2 are cleared to 0, the column address output cycle ends in 1 state and no wait states are inserted. When the bit is 1, the WAIT pin input signal is sampled on the rise of the system clock (CK) directly preceding the second state of the column address output cycle and the wait state is inserted as long as the level is low. When a high level is detected, it shifts to the second state. Figure 8.20 shows the wait state timing in a long pitch bus cycle.
Tp
CK
Tr
Tc 1
Tcw (wait state)
Tc2
A21-A0
Row address
Column address
RAS
CAS
WAIT
Figure 8.20 Wait State Timing during DRAM Access (Long Pitch)
RENESAS 139
When the RW1 bit is set to 1, the number of wait states selected by CBR refresh wait state insertion bits 1 and 0 (RLW1, RLW0) of the refresh control register (RCR) are inserted into the CAS-before-RAS refresh cycle. 8.5.4 Byte Access Control
16-bit width and 18-bit width DRAMs require different types of byte control signals for access. By setting the dual CAS signals/dual WE signals select bit (CW2) in the DCR, the BSC allows selection of either the dual CAS signals or the dual WE signals system of control signals. When 16-bit space is being accessed and the CW2 bit is cleared to 0 for dual CAS signals, CASH, CASL, and WRL signals are output; when CW2 is set to 1 for dual WE signals, the CASL, WRH, and WRL signals are output. When accessing 8-bit space, WRL and CASL are output regardless of the CW2 setting. Figure 8.21 shows the control timing of the upper byte write cycle (short pitch) in 16-bit space.
140 RENESAS
Tp
CK
Tr
Tc
A21-A0
Row address
Column address
RAS
Byte control
CASH
CASL WRH WRL
High level High level fixed
(a) Dual CAS signals (CW2 = 0)
Tp
CK
Tr
Tc
A21-A0 RAS CASH CASL WRH WRL
Row address
Column address
High level fixed
Byte control
High level (a) Dual WE signals (CW2 = 1)
Figure 8.21 Byte Access Control Timing for DRAM Access (Upper Byte Write Cycle, Short Pitch)
RENESAS 141
8.5.5
DRAM Burst Mode
In addition to the normal mode of DRAM access, in which row addresses are output at every access and data then accessed (full access), the DRAM also has a high-speed page mode for use when continuously accessing the same row. The high speed page mode enables fast access of data simply by changing the column address after the row address is output (burst mode). Select between full access and burst operation by setting the burst enable bit (BE)) in the DCR. When the BE bit is set to 1, burst operation is performed when the row address matches the previous DRAM access row address. Figure 8.22 shows the comparison of full access and burst operation.
RAS CAS
Column address 1
Column address 2
A21-A0 AD15- AD0
Row address 1 Data 1 (a) Full access (read cycle) Row address 2 Data 2
RAS CAS
Column Column Column Column address 1 address 2 address 3 address 4
A21-A0 AD15- AD0
Row address 1 Data 1 Data 2 Data 3 Data 4 (b) Burst operation (read cycle)
Figure 8.22 Full Access and Burst Operation Short pitch high-speed page mode or long pitch high-speed page mode burst transfers can be selected independently for DRAM read/write cycles even when the burst operation is selected by using the bits corresponding to area 1 in WCR1 and WCR2 (RW1, WW1, DRW1, DWW1). The RAS down mode or RAS up mode can be selected by setting the RAS down bit (RASD) of the DCR when there is an access outside the DRAM space during burst operation.
142 RENESAS
Short Pitch High-Speed Page Mode and Long Pitch High-Speed Page Mode: When burst operation is selected by setting the DCR's BE bit to 1, the short pitch high-speed page mode or long pitch high-speed page mode can be selected by setting the RW1, WW1, DRW1, and DWW1 bits of the WCR1 and WCR2. * Short-pitch, high-speed page mode: When the RW1, WW1, DRW1 and DWW1 bits in the WCR1 and WCR2 are cleared to 0, and the corresponding DRAM access cycle is continuing, the CAS signal and column address output cycles continue as long as the row addresses continue to match. The column address output cycle is performed in 1 state and the WAIT signal is not sampled. Figure 8.23 shows the read cycle timing for the short pitch high-speed page mode.
Tp
Tr
Tc
Tc
Tc
Tc
CK Column address 1 A21- A0 Row address 1 RAS CAS WR AD15- A0 Data 1 Data 2 Data 3 Data 4 Column address 2 Column Column address 3 address 4
Figure 8.23 Short Pitch High-Speed Page Mode (Read Cycle) When the write cycle continues for the same row address in the short pitch high-speed page mode, an open cycle (silent cycle) is produced for 1 cycle only. This timing is shown in figure 8.24. Likewise, when a write cycle continues after the read cycle for the same row address, a silent cycle is produced for 1 cycle. This timing is shown in figure 8.25. Note also that when DRAM is written to in short-pitch, high-speed page mode when using DMAC single address mode, a silent cycle is inserted in each transfer. The details of timing are discussed in section 20.3.3, Bus Timing.
RENESAS 143
Access A Tp Tr Tc Tc Silent cycle
Access B Tc Tc
CK Column Column address A-1 address A-2 A21- A0 Row address RAS CAS WR AD15- A0 Data A-1 Data A-2 Data B-1 Data B-2 Column Column address B-1 address B-2
Note: Access A and B are examples of 32-bit data accesses in their respective 16-bit bus width spaces.
Figure 8.24 Short Pitch High-Speed Page Mode (Write Cycle)
144 RENESAS
Access A (read) Tp Tr Tc Tc
Access B (write) Silent cycle Tc Tc
CK
Column Column address A-1 address A-2 Column Column address B-1 address B-2
A21- A0
Row address
RAS CAS WR AD15- AD0
Read data A-1 Read data A-2 Write data B-1 Write data B-2 Note: Access A and B are examples of 32-bit data accesses in their respective 16-bit bus width spaces.
Figure 8.25 Short Pitch High-Speed Page Mode (When read and write cycle continues with the same row address) The high-level duty of the CAS signal can be selected in the short pitch high-speed page mode using the CAS duty bit (CDTY) in the DCR. When the CDTY bit is cleared to 0, high-level duty is 50% of the TC state; when CDTY is set to 1, it is 35% of the TC state. * Long-pitch, high-speed page mode: When the RW1, WW1, DRW1, and DWW1 bits in WCR1 and WCR2 are set to 1, and the corresponding DRAM access cycle is continuing, the CAS signal and column address output cycles (2 states) continue as long as the row addresses continue to match. When the WAIT signal is detected at the low level, the second cycle of the column address output cycle is repeated as the wait state. Figure 8.26 shows the timing for the long pitch high-speed page mode. See section 20.3.3, Bus Timing, for more information about the timing.
RENESAS 145
Tp
Tr
Tc1
Tc2
Tc1
Tc2
CK A21-AD0
Row address 1
Column address 1 Column address 2
RAS CAS
Read
WR AD15-AD0 WR
Data 1 Data 2
Write
AD15-AD0
Data 1
Data 2
Figure 8.26 Long Pitch High-Speed Page Mode (Read/Write Cycle) RAS Down Mode and RAS Up Mode: Sometimes access to another area can occur between accesses to the DRAM even though burst operation has been selected. Keeping the RAS signal at low while this other access is occurring allows burst operation to continue the next time the same row of the DRAM is accessed. The RASD bit in the DCR selects the RAS down mode when set to 1 and the RAS up mode when cleared to 0. In both RAS down mode and RAS up mode, burst operation is continued while the same row address continues to be accessed, even if the bus master is changed. * RAS Down Mode: When the RASD bit of DCR is set to 1, the DRAM access pauses and the RAS signal is held low throughout the access of the other space while waiting for the next access to the DRAM area. When the row address for the next DRAM access is the same as the previous DRAM access, burst operation continues. Figure 8.27 shows the timing of the RAS down mode when external memory space is accessed during burst operation. The RAS signal can be held down in the DRAM for a limited time; the RAS signal must be returned to high within the specified limits even when the RAS down mode is selected since the critical low level period is set. In this LSI, even when the RAS down mode is selected, the RAS signal automatically reverts to high when the DRAM is refreshed, so the BSC's refresh control function can be employed to set a CAS-before-RAS refresh that will keep operation within specifications. See section 8.5.6, Refresh Control, for details.
146 RENESAS
DRAM access
Tp Tr Tc Tc
External memory space access
T1
DRAM access
Tc Tc
CK
Column Column address 1 address 2 External Column Column memory address 3 address 4
A21- A0
Row address
RAS CAS WR AD15- AD0 Data 1 Data 2
External memory data
Data 3
Data 4
Figure 8.27 RAS Down Mode * RAS Up Mode: When the RASD bit is cleared to 0, the RAS signal reverts to high whenever a DRAM access pauses for access to another space. Burst operation continues only while DRAM access is continuous. Figure 8.28 shows the timing when an external memory space access occurs during burst operation in the RAS up mode.
RENESAS 147
DRAM access
Tp Tr Tc Tc
External memory space access
T1
DRAM access
Tr Tc
Tp
CK
Column Column External memory address 1 address 2 address Column address 3
A21- A0
Row address Row address
RAS CAS AD15- AD0
Data 1
Data 2
External memory data
Data 3
Figure 8.28 RAS Up Mode 8.5.6 Refresh Control
The BSC has a function for controlling DRAM refreshing. By setting the refresh mode bit (RMODE) in the refresh control register (RCR), either CAS-before-RAS refresh (CBR) or selfrefresh can be selected. When no refresh is performed, the refresh timer counter (RTCNT) can be used as an 8-bit interval timer. CAS-Before-RAS Refresh (CBR): A refresh is performed at an interval determined by the input clock selected in the clock select bits 2-0 (CKS2-CKS0) of the refresh timer control/status register (RTCSR) and the value set in the refresh time constant register (RTCOR). Set the values of RTCOR and CKS2-CKS0 so they satisfy the refresh interval specifications of the DRAM being used. To perform a CBR refresh, clear the RMODE bit of the RCR to 0 and then set the refresh control bit (RFSHE) bit to 1. Also write in the required values to RTCNT and RTCOR. When the clock is thereafter selected in the CKS2-CKS0 bits of the RTCSR, the RTCNT will begin to increment from its current value. The RTCNT value is constantly compared to the RTCOR value and the CBR refresh is performed when they match. The RTCNT is simultaneously cleared to H'00 and incrementing begins again. When the clock is selected in the CKS2-CKS0 bits, the RTCNT immediately begins to increment from its current value. This means that when the RTCOR cycle is set after the CKS2-CKS0 bits are set, the RTCNT count may already be higher than the RTCOR cycle. When this occurs, the RTCNT will overflow once (H'FF goes to H'00) and incrementing will start again. Since the CBR
148 RENESAS
refresh will not be performed until the RTCNT again matches the RTCOR value, the initial refresh interval will be rather long. It is thus advisable to set the RTCOR cycle prior to setting the CKS2- CKS0 bits and start it incrementing. When CBR refresh control is being performed after its use as an 8-bit interval timer, the RTCNT count value may be in excess of the refresh cycle. For this reason, clear the RTCNT by writing H'00 before starting refresh control to assure a correct refresh interval. When the RW1 bit of WCR1 is set to 1 and the read cycle is set to long pitch, the number of wait states selected by the RLW1 and RLW0 bits of the RCR will be inserted into the CBR refresh cycle, regardless of the status of the WAIT signal. Figure 8.29 shows the RTCNT operation and figure 8.30 shows the timing of the CBR refresh. For details on timing, see section 20.3.3, Bus Timing.
RTCNT value RTCOR value
Compare match with RTCOR
Compare match with RTCOR
Compare match with RTCOR
Compare match with RTCOR
H'00 Clock CBR selected with CKS2-CKS0 CBR CBR CBR
Time
CBR: CAS-before-RAS refresh
Figure 8.29 Refresh Timer Counter (RTCNT) Operation
TRp
TRr
TRc
CK
RAS CAS
Figure 8.30 Output Timing for CAS-Before-RAS Refresh Signal Self-Refresh Mode: Some DRAMs have a self-refresh mode (parity back-up mode). This is a type of a standby mode in which the refresh timing and refresh addresses are generated inside the DRAM chip. When the RFSHE and RMODE bits of the RCR are both set to 1, the DRAM will
RENESAS 149
enter the self-refresh mode when the CAS and RAS signals are output as shown in figure 8.31. See section 20.3.3, Bus Timing, for details. The DRAM self-refresh mode is cleared when the RMODE bit in the RCR is cleared to 0 (figure 8.31). The RFSHE bit should be left at 1 when this is done. Some DRAM vendors recommend that after exiting the self-refresh mode, all row addresses should be refreshed again. This can be done using the BCR's CBR refresh function to set all row addresses for refresh in software. To access a DRAM area in the self-refresh mode, clear the RMODE bit to 0 and exit the selfrefresh mode. The LSI can be kept in the self-refresh state and shifted to standby mode by setting it to selfrefresh mode, setting the standby bit (SBY) of the standby control register (SBYCR) to 1, and then executing a SLEEP instruction.
TRp
TRr
TRc
TRcc
CK
RAS CAS
Figure 8.31 Output Timing of Self-Refresh Signal Refresh Requests and Bus Cycle Requests: When a CAS-before-RAS refresh or self-refresh is requested during bus cycle execution, parallel execution is sometimes possible. Table 8.10 describes operation when the refresh and bus cycle are in contention.
150 RENESAS
Table 8.10 Refresh and Bus Cycle Contention
Type of Bus Cycle External Space Access On-Chip ROM, On-Chip RAM , On-Chip Read Cycle Write Cycle Read Cycle Write Cycle Peripheral Access DRAM Space Yes Yes No Yes No No No No Yes Yes External Memory Space, Multiplexed I/O Space
Type of Refresh CAS-beforeRAS refresh Self-refresh
Yes: Can be executed in parallel No: Cannot be executed in parallel
When parallel execution is available, the RAS and CAS signals are output simultaneously during bus cycle execution and the refresh is executed. When parallel execution is not available, refresh occurs after the bus cycle has ended. Using RTCNT as an 8-Bit Interval Timer: When not performing refresh control, RTCNT can be used as an 8-bit interval timer. Simply set the RFSHE bit of the RCR to 0. To produce a compare match interrupt (CMI), set the compare match interrupt enable bit (CMIE) to 1 and set the interrupt generation timing in RTCOR. When the input clock is selected with the CKS2-CKS0 bits of the RTCSR, RTCNT starts incrementing as an 8-bit interval timer. Its value is constantly being compared to RTCOR and when a match occurs, the CMF bit of RTCSR is set to 1 and a CMI interrupt is produced. RTCNT is cleared to H'00. When the clock is selected with CKS2-CKS0 bits, RTCNT starts incrementing immediately. This means that when the RTCOR cycle is set after the CKS2-CKS0 bits are set, the RTCNT count may already be higher than the RTCOR cycle. When this occurs, the RTCNT will overflow once (H'FF goes to H'00) and the count up will start again. No interrupt will be generated until the RTCNT again matches the RTCOR value. It is thus advisable to set the RTCOR cycle prior to setting the CKS2-CKS0 bits. After its use as an 8-bit interval timer, the RTCNT count value may be in excess of the set cycle. For this reason, write H'00 to the RTCNT to clear it before starting to use it again with new settings. RTCNT can then be restarted and an interrupt obtained after the correct interval.
8.6
Address/Data Multiplexed I/O Space Access
The BSC is equipped with a function that multiplexes input/output of address and data to pins AD15-AD0 in area 6. This allows the SH microprocessor to be directly connected to peripheral LSIs that required address/data multiplexing.
RENESAS 151
8.6.1
Basic Timing
When the multiplexed I/O enable bit (IOE) of the BCR is set to 1, the area 6 space with address bit A27 as 0 (H'6000000-H'6FFFFFF) becomes an address/data multiplexed I/O space that, when accessed, multiplexes addresses and data. When the A14 address bit is 0, the bus width is 8 bits and address output and data input/output are performed from the AD7-AD0 pins. When the A14 address bit is 1, the bus width is 16 bits and address output and data input/output are performed from the AD15-AD0 pins. In the address/data multiplexed I/O space, access is controlled with the AH, RD and WR signals. Accesses in the address/data multiplexed I/O space is performed in 4 states, regardless of the WCR settings. Figure 8.32 shows the timing when the address/data multiplexed I/O space is accessed.
T1
T2
T3
T4
CK A21-A0
CS
AH RD
Read
AD15-AD0 WRH, WRL
Write
Address
Data (input)
AD15-AD0
Address
Data (output)
Figure 8.32 Access Timing For Address/Data Multiplexed I/O Space The high-level duty of the RD signal can be selected between 35% and 50% using the RD duty bit (RDDTY) of the BCR. When RDDTY is 1, the high-level duty is 35% of the T3 or Tw state, lengthening the access time for external devices.
152 RENESAS
8.6.2
Wait State Control
When the address/data multiplexed I/O space is accessed, the WAIT pin input signal is sampled and a wait state inserted whenever a low level is detected, regardless of the setting of the WCR. Figure 8.33 shows an example in which a WAIT signal causes a wait state of 1 state to be inserted.
T1
CK A21-A0
T2
T3
Tw (wait state)
T4
CS AH
RD
Read
AD15-AD0 Address Data (input)
WRH, WRL
Write
AD15-AD0 Address Data (output)
WAIT
Figure 8.33 Wait State Timing For Address/Data Multiplexed I/O Space Access 8.6.3 Byte Access Control
The byte access control signals when the address/data multiplexed I/O space is being accessed are of two types (WRH, WRL, A0, or WR, HBS, LBS), just as for byte access control of external memory space access. These types can be selected using the BAS bit of the BCR. See section 8.4.3, Byte Access Control, for details.
RENESAS 153
8.7
Parity Check and Generation
The BSC can check and generate parity for data input and output to or from in the DRAM space of area 1 and the external memory space of area 2. To check and generate parity, select the space (DRAM space only, or DRAM space and area 2) for which parity is to be checked and generated using the parity check enable bits (PCHK1 and PCHK0) of the parity control register and select odd or even parity in the parity polarity bit (PEO). When data is input from the space selected in the PCHK1 and PCHK0 bits, the BSC checks the PEO bit to see if the polarity of the DPH pin input (upper byte parity data) is accurate for the AD15-AD8 pin input (upper byte data) or if the DPL pin input (lower byte parity data) is accurate for the AD7-AD0 pin input (lower byte data). If the check indicates that either the upper or lower byte parity is incorrect, a parity error interrupt is produced (PEI). When outputting data to the space selected in the PCHK1 and PCHK0 bits, the BSC outputs parity data output of the polarity set in the PEO bit from the DPH pin for the AD15-AD8 pin output (upper byte data) or from the DPL pin for the AD7-AD0 pin input (lower byte data) using the same timing as the data output. The BSC is also able to force a parity output for use in testing the system's parity error check function. When the parity force output bit (PFRC) of the PCR is set to 1, a high level is forcibly output from the DPH and DPL pins when data is output to the space selected in the PCHK1 and PCHK0 bits.
8.8
Warp Mode
In warp mode, an external write cycle or DMA single address mode transfer cycle and an internal access cycle (read/write to on-chip memory or on-chip peripheral modules) operate independently in parallel. The warp mode is entered by setting the warp mode bit (WARP) in the BCR to 1. This allows the LSI to be operated at high speed. When in the warp mode an external write cycle or DMA single address mode transfer cycle continues for at least 2 states and their is an internal access, only the external write cycle will be performed in the initial state. The external write cycle and internal access cycle will be performed in parallel from the next state on, without waiting for the end of the external write cycle. Figure 8.34 shows the timing when an access to an on-chip peripheral module and an external write cycle are performed in parallel.
154 RENESAS
External space writing On-chip peripheral module read/write
T1
CK A21- A0 External space write CSn
T2
T3
T4
T5
External space address
WR AD15- AD0
Write data
External space address
On-chip peripheral module address
Internal address On-chip peripheral module write On-chip peripheral module read Internal write strobe Internal data bus Internal read strobe Internal data bus
Write data
Read data
Figure 8.34 Warp Mode Timing (Access to On-Chip Peripheral Module and External Write Cycle)
8.9
Wait State Control
The WCR1-WCR3 registers of the BSC can be set to control sampling of the WAIT signal when accessing various areas and the number of bus cycle states. Table 8.11 shows the number of bus cycle states when accessing various areas.
RENESAS 155
Table 8.11 Bus Cycle States when Accessing Address Spaces
CPU Read Cycle, DMAC Dual Mode Read Cycle, DMAC Single Mode Memory Read/Write Cycle Address Space External memory (areas 1, 3-5, 7) External memory (Areas 0, 2, 6; long wait available) DRAM space (area 1) Corresponding Bits in WCR1 and WCR2 = 0 Corresponding Bits in WCR1 and WCR2 = 1
1 state fixed; WAIT signal ignored 2 states + wait states from WAIT signal 1 state + long wait state*, WAIT signal ignored Column address cycle: 1 state, WAIT signal ignored (short pitch) 1 state + long wait state* + wait states from WAIT signal Column address cycle: 2 states + wait states from WAIT signal (long pitch)
Multiplexed I/O space (area 6) On-chip peripheral module space (area 5) On-chip ROM (area 0) On-chip RAM (area 7)
4 states + wait states from WAIT signal 3 states fixed, WAIT signal ignored 1 state fixed, WAIT signal ignored 1 state fixed, WAIT signal ignored
CPU Write Cycle, DMAC Dual Mode Memory Write Cycle Address Space External memory (areas 1, 3-5, 7) External memory (Areas 0, 2, 6; long wait available) DRAM space (area 1) WW1 of WCR1 = 0 WW1 of WCR1 =1
2 states + wait states from WAIT signal 1 state + long wait state* + wait states from WAIT signal
Column address cycle: 1 state, WAIT signal ignored (short pitch)
Column address cycle: 2 states + wait states from WAIT signal (long pitch)
Multiplexed I/O space (area 6) On-chip peripheral module space (area 5) On-chip ROM (area 0) On-chip RAM (area 7)
4 states + wait states from WAIT signal 3 states fixed, WAIT signal ignored 1 state fixed, WAIT signal ignored 1 state fixed, WAIT signal ignored
Note: The number of long wait states (1 to 4) is set in WCR3.
156 RENESAS
For details on bus cycles when external spaces are accessed, see section 8.4, External Memory Space Access, section 8.5, DRAM Space Access, and section 8.6, Address/Data Multiplexed I/O Space Access. Accesses of on-chip spaces are as follows: On-chip peripheral module spaces (area 5 when address bit A27 is 1) are always 3 states, regardless of the WCR, with no WAIT signal sampling. Accesses of on-chip ROM (area 0 when MD2-MD0 are 010) and on-chip RAM (area 7 when address bit A27 is 0) are always performed in 1 state, regardless of the WCR, with no WAIT signal sampling. If the bus timing specifications (tWTS and tWTH) are not observed when the WAIT signal is input in external space access, this will simply mean that WAIT signal assertion and negation will not be detected, but will not result in misoperation. Note, however, that the inability to detect WAIT signal assertion may result in a problem with memory access due to insertion of an insufficient number of waits.
8.10
Bus Arbitration
The SuperH microcomputer can release the bus to external devices when they request the bus. It has two internal bus masters, the CPU and the DMAC. Priorities for releasing the bus for these two are as follows. Bus request from external device > refresh > DMAC > CPU Thus, an external device has priority when it generates a bus request, even when the DMAC is doing a burst transfer. Note that when a refresh request is generated while the bus is released to an external device, BACK becomes high level and the bus right can be acquired to perform the refresh upon receipt of a BREQ = high level response from the external device. Input all bus requests from external devices to the BREQ pin. The signal indicating that the bus has been released is output from the BACK pin. Figure 8.35 illustrates the bus release procedure.
RENESAS 157
SuperH BREQ = low BREQ received Strobe pin: High-level output Address, data, strobe pin: High impedance Bus release response BACK = low
External device Bus request
BACK acknowledge
Bus acquisition
Bus released
Figure 8.35 Bus Release Procedure 8.10.1 The Operation of Bus Arbitration
This LSI has the bus arbitration function which can give bus ownership to an external device when the device requests the bus ownership. When BREQ is input and the bus cycle being executed by the CPU or DMAC is completed, BACK becomes low and a bus is released for an external device. At this time, the following operates when bus arbitration conflicts with refresh. 1. If DRAM refresh is requested in this LSI when a bus is released and BACK is low, BACK becomes high and the occurrence of the refresh request can be informed externally. At this time, the external device may generate a bus cycle when BREQ is low even if BACK is high. Therefore, a bus remains released to the external device. Then, when BREQ becomes high, this LSI gets bus ownership, and executes refresh and the bus cycle of the CPU or DMAC. After the external device gets bus ownership and BACK is low, refresh is requested when BACK becomes high even if the low level of BREQ is input. Therefore, turn BREQ high immediately to release a bus for this LSI to hold DRAM data (See figure 8.36). 2. When BREQ changes from high to low and internal refresh is requested at the timing of the bus release of this LSI, BACK may remain high (do not become low). A bus is released to the external device since the low level of BREQ is input. This operation is based on the above specification (1). To hold DRAM data, turn BREQ high and release a bus to this LSI immediately when the external device detects that BACK does not change to low during a fixed time this LSI (See figure 8.37). When a refresh request is generated and BACK returns to high, as shown in figure 8.37, a momentary narrow pulse-shaped spike may be output where BACK was originally supposed to become low.
158 RENESAS
BREQ BACK
Refresh execution
Refresh damand
Figure 8.36 BACK Operation by Refresh Demand (1)
If BACK has not gone low after waiting for the maximum number of states* before the SuperH releases the bus, return BREQ to the high level.
BREQ BACK
BACK does not go low. Refresh request Note: * For details see section 8.11.3, Maximum Number of States from BREQ Input to Bus Release.
Figure 8.37 BACK Operation in Response to Refresh Request (2) 8.10.2 BACK Operation
1. BACK Operation When an internal refresh is requested during an attempt to assert the BACK signal and BACK is not asserted but remains high, a momentary narrow pulse-shaped spike may be output, as shown below.
BREQ BACK pulse width of the spike is approx. 2 to 5 ns. Refresh demand
RENESAS 159
2. Countermeasure against a spike on the BACK signal The following describes the countermeasure against a spike on the BACK signal: a. When BREQ is input to release the bus of the LSI, make sure that conflicts with a refresh operation do not occur. Stop the refresh operation or operate the refresh timer counter (RTCNT) or the refresh time constant register (RTCOR) of the bus controller (BSC) to shift the refresh timing. b. The spike on the BACK signal has a narrow pulse width of approximately 2 to 5 ns, which can be eliminated by using a capacitor as shown in the figure below. For example, adding a capacitance of 220 pF can raise the minimum voltage of the spike above 2.0 V. Note that delay of the BACK signal increases approximately in units of 0.1 ns/pF. (When a capacitance of 220 pF is added, the delay increases approximately by 22 ns.
BACK C SuperH Microcomputer Capacitor-incorporating circuit for eliminating a spike
c. Latching the BACK signal by using a flip-flop or triggering the flip-flop may be successful or unsuccessful due to the narrow pulse width of the spike. Implement a circuit configuration which will cause no problems when latching BACK or using BACK as a trigger signal. When splitting the BACK signal into two signals and latching each of them using the flipflop or triggering the flip-flop, the flip-flop may operate for one signal but may not for another. To capture the BACK signal using the flip-flop, receive the BACK signal using a single flip-flop then distribute the signal (see figure below).
160 RENESAS
Trigger OK DQ BACK Q Trigger NG DQ Q DQ BACK Q
8.11
8.11.1
Usage Notes
Usage Notes on Manual Reset
Condition: When DRAM (long-pitch mode) is used and manual reset is performed. The low width of RAS output may be shorter than usual in rese + (2.5tcyc1.5tcyc), causing the specified value (tRAS) of DRAM not to be satisfied.
Corresponding DRAM conditions: long pitch/normal mode long pitch/high-speed page mode
There are no problems regarding operations except for the above conditions. There are the following four cases (Figure 8.38 to Figure 8.41) for the output states of DRAM control signals (RAS, CAS, and WR) corresponding to RES latch timing. Actual output levels are shown by solid lines (not by dashed lines).
RENESAS 161
RES latch timing
Tp
Tr
Tc1
Tc2
CK RES A0 to A21 RAS CAS WR AD0 to AD15
Data output Manual reset
Row address Colum address
FFFF
Figure 8.38 Long - pitch Mode Write (1)
RES latch timing
Tp
Tr
Tc1
Tc2
CK RES A0 to A21 RAS CAS WR AD0 to AD15
Data output Manual reset
Row address
FFFF
Figure 8.39 Long - pitch Mode Write (2)
162 RENESAS
RES latch timing CK RES A0 to A21 RAS CAS RD
Tp
Tr
Tc1
Tc2
Manual reset
Row address Colum address FFFF
Figure 8.40 Long - pitch Mode Read (1)
RES latch timing CK RES A0 to A21 RAS CAS RD
Manual reset
Tp
Tr
Tc1
Tc2
Row address
FFFF
Figure 8.41 Long - pitch Mode Read (2) For the signal output shown by solid lines, DRAM data may not be held. Therefore, when DRAM data must be held after reset, take one of the coutermeasures described as follows. 1. When resetting manually, do this in watchdog timer (WDT) condition. 2. Even if the Low width of RAS becomes as short as 1.5 tcyc as shown above, use with a frequency that satisfies the DRAM standard (tRAS). 3. Even in case the Low width of RAS has become 1.5 tcyc, proceed by using the external circuit so that a RAS signal with a Low width of 2.5 tcyc is input in the DRAM (in case the Low width of RAS is higher than 2.5 tcyc, operate so that the current waveform is input in the DRAM).
RENESAS 163
The countermeasures are not required when DRAM data is initialized or loaded again after manual reset. 8.11.2 Usage Notes on Parity Data Pins DPH and DPL
The following specifies the setup time tDS of the parity dada DPH and DPL to CAS signal rising when the parity dada DPH and DPL are written to DRAM in long-pitch mode (early write). Table 8.12 Setup Time of Parity Data DPH and DPL
Item Data setup time to CAS (for only DPH and DPL in long-pitch mode) Symbol tDS min -5 ns
Therefore, when writing parity data DPH and DPL to the DRAM in long-pitch mode, delay the WRH and WRL signals of this LSI and write with delayed writing. Nomal dada is also delayed-written, causing no problems.
SuperH
RAS RD *1 *1 D *2 Q Q
RAS CAS OE DWRH or DWRL WE
DRAM
Microcomputer CAS
WRH or WRL CK
*1: For preventing signal racing *2: Negative edge latch
Figure 8.42 Delayed-Write Control Circuit 8.11.3 Maximum Number of States from BREQ Input to Bus Release
The maximum number of states from BREQ input to bus release is: Maximum number of states for which bus is not released + approx. 4.5 states Note: Breakdown of approx. 4.5 states: 1.5 states: Until BACK output after end of bus cycle 1 state (min.): tBACD1 1 state (max.): tBRQS 1 state: Sampling in 1 state before end of bus cycle
164 RENESAS
BREQ is sampled one state before the bus cycle. If BREQ is input without satisfying tBRQS, the bus is released after executing cycle B following the end of bus cycle A, as shown in figure 8.43. The maximum number of states from BREQ input to bus release are used when B is a cycle comprising the maximum number of states for which the bus is not released; the number of states is the maximum number of states for which bus is not released + approx. 4.5 states. The maximum number of states for which the bus is not released requires careful investigation.
CK Bus cycle A B
BREQ tBRQS BACK tBACD1 Bus release
Figure 8.43 When BREQ is Input without Satisfying tBRQS 1. Cycles in which bus is not released (a) One bus cycle The bus is never released during one bus cycle. For example, in the case of a longword read (or write) in 8-bit ordinary space, one bus cycle consists of 4 memory accesses to 8-bit ordinary space, as shown in figure 8.44. The bus is not released between these accesses. Assuming one memory access to require 2 states, the bus is not released for a period of 8 states.
8 bits 8 bits 8 bits 8 bits Cycle during which bus is not released
Figure 8.44 One Bus Cycle (b) TAS instruction read cycle and write cycle The bus is never released during a TAS instruction read cycle and write cycle (figure 8.45). The TAS instruction read cycle and write cycle should be regarded as one bus cycle during which the bus is not released.
RENESAS 165
Read cycle
Write cycle
Cycle during which bus is not released (1 bus cycle)
Figure 8.45 TAS Instruction Read Cycle and Write Cycle (c) Refresh cycle + bus cycle The bus is never released during a refresh cycle and the following bus cycle ((a) or (b) above)) (figure 8.46).
Refresh cycle
1 bus cycle
Cycle during which bus is not released
Figure 8.46 Refresh Cycle and Following Bus Cycle
166 RENESAS
2. Bus release procedure The bus release procedure is shown in figure 8.47. Figure 8.47 shows the case where BREQ is input one state before the break between bus cycles so that tBRQS is satisfied. In the SH7020 and SH7021, the bus is released after the bus cycle in which BREQ is input (if BREQ is input between bus cycles, after the bus cycle starting next).
CK tBRQS BREQ tBACD1 BACK tBZD RD, WR RAS, CAS CSn A21 to A0 tBRQS tBACD1
tBZD
Bus cycle
Bus release
Bus cycle
Strobe pin: high-level output
Address & data strobe pins: high impedance Bus cycle restart
The bus is released after the bus cycle in which BREQ is input (if BREQ is input between bus cycles, after the bus cycle starting next).
Figure 8.47 Bus Release Procedure
RENESAS 167
Section 9 Direct Memory Access Controller (DMAC)
9.1 Overview
The SuperH microprocomputer chip includes a four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, memory-mapped external devices, on-chip memory and on-chip peripheral modules (excluding the DMAC itself). Using the DMAC reduces the burden on the CPU and increases overall operating efficiency. 9.1.1 Features
The DMAC has the following features. * * * * * Four channels Four Gbytes of address space on the architecture Byte or word selectable data transfer unit 65536 transfers (maximum) Single address mode transfers (channels 0 and 1): Either the transfer source or transfer destination (peripheral device) is accessed by a DACK signal (selectable) while the other is accessed by address. 1 transfer unit of data is transferred in each bus cycle. Device combinations able to transfer: External devices with DACK and memory-mapped external devices (including external memories) External devices with DACK and memory-mapped external memories Dual address mode transfer: (channels 0-3): Both the transfer source and transfer destination are accessed by address. 1 transfer unit of data is transferred in 2 bus cycles. Device combinations able to transfer: Two external memories External memory and memory-mapped external devices Two memory-mapped devices External memory and on-chip memory Memory-mapped external devices and on-chip peripheral module (excluding the DMAC itself) External memory and on-chip memory Memory-mapped external device and on-chip peripheral module (excluding the DMAC) Two on-chip memories On-chip memory and on-chip peripheral modules (excluding DMAC)
RENESAS 169
*
*
* * * *
Two on-chip peripheral modules (excluding DMAC) Transfer requests External request (From DREQ pins (channels 0 and 1 only). DREQ can be detected either by edge or by level) Requests from on-chip peripheral modules (serial communications interface (SCI), and 16bit integrated-timer pulse unit (ITU)) Auto-request (the transfer request is generated automatically within the DMAC) Selectable bus modes: Cycle-steal mode or burst mode Selectable channel priority levels: Fixed, round-robin, or external-pin round-robin modes CPU can be asked for interrupt when data transfer ends Maximum transfer rate 20 M words/s (320 MB/s) For 5V and 20 MHz Bus mode: Burst mode Transmit size: Word Block Diagram
9.1.2
Figure 9.1 is a block diagram of the DMAC.
170 RENESAS
Peripheral bus
Internal bus
Register control Start-up control
CHCRn
DREQ0, DREQ1 ITU SCI
DMAOR
DACK0, DACK1 DEIn
External ROM External RAM External device (memory mapped) External device (with acknowledge)
Request priority control
External bus
Bus interface
Bus controller
DMAC
DMAOR: DMA operation register SARn: DMA source address register DARn: DMA destination address register TCRn: DMA transfer count register CHCRn: DMA channel control register DEIn: DMA transfer-end interrupt request to CPU. n: 0-3
Figure 9.1 DMAC Block Diagram
RENESAS 171
DMAC module bus
On-chip ROM On-chip RAM On-chip peripheral module
SARn DARn Iteration control TCRn
9.1.3
Pin Configuration
Table 9.1 shows the DMAC pins. Table 9.1
Channel 0
Pin Configuration
Name DMA transfer request DMA transfer request acknowledge Symbol DREQ0 DACK0 I/O I O Function DMA transfer request input from external device to channel 0 DMA transfer request acknowledge output from channel 0 to external device DMA transfer request input from external device to channel 1 DMA transfer request acknowledge output from channel 1 to external device
1
DMA transfer request DMA transfer request acknowledge
DREQ1 DACK1
I O
172 RENESAS
9.1.4
Register Configuration
Table 9.2 summarizes the DMAC registers. DMAC has a total of 17 registers. Each channel has four control registers. One other control register is shared by all channels Table 9.2
Channel 0
DMAC Registers
Abbreviation SAR0*3 DAR0* 3 TCR0*3 CHCR0 SAR1*3 DAR1* 3 TCR1*3 CHCR1 SAR2*3 DAR2* 3 TCR2*3 CHCR2 SAR3*3 DAR3* 3 TCR3*3 CHCR3 DMAOR R/W R/W R/W R/W R/(W)*1 R/W R/W R/W R/(W)*1 R/W R/W R/W Initial Value Address Access Size 16, 32 16, 32
Name DMA source address register 0 DMA destination address register 0 DMA transfer count register 0 DMA channel control register 0
Undefined H'5FFFF40 Undefined H'5FFFF44
Undefined H'5FFFF4A 16, 32 H'0000 H'5FFFF4E 8, 16, 32 16, 32 16, 32
1
DMA source address register 1 DMA destination address register 1 DMA transfer count register 1 DMA channel control register 1
Undefined H'5FFFF50 Undefined H'5FFFF54
Undefined H'5FFFF5A 16, 32 H'0000 H'5FFFF5E 8, 16, 32 16, 32 16, 32
2
DMA source address register 2 DMA destination address register 2 DMA transfer count register 2 DMA channel control register 2
Undefined H'5FFFF60 Undefined H'5FFFF64
Undefined H'5FFFF6A 16, 32 H'5FFFF6E 8, 16, 32 16, 32 16, 32
R/(W)*1 H'0000 R/W R/W R/W R/(W)*1 R/(W)*2
3
DMA source address register 3 DMA destination address register 3 DMA transfer count register 3 DMA channel control register 3
Undefined H'5FFFF70 Undefined H'5FFFF74
Undefined H'5FFFF7A 16, 32 H'0000 H'0000 H'5FFFF7E 8, 16, 32 H'5FFFF48 8, 16, 32
Shared DMA operation register
Notes: 1. Write 0 alone in bit 1 of CHCR0-CHCR3 to clear flags. 2. Write 0 alone in bits 1 and 2 of the DMAOR to clear flags. 3. Access SAR0-SAR3, DAR0-DAR3, and TCR0-TCR3 by long word or word. If byte access is used when writing, the value of the register contents becomes undefined; if used when reading, the value read is undefined.
RENESAS 173
9.2
9.2.1
Register Descriptions
DMA Source Address Registers 0-3 (SAR0-SAR3)
DMA source address registers 0-3 (SAR0-SAR3) are 32-bit read/write registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address (in single-address mode, SAR is ignored in transfers from external devices with DACK to memory-mapped external devices or external memory). The initial value after resets or in standby mode is undefined.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W 23 -- R/W 22 -- R/W 21 -- R/W 20 -- R/W -- R/W ... ... ... ... -- R/W -- R/W -- R/W 0 31 30 29 28 27 26 25 24
9.2.2
DMA Destination Address Registers 0-3 (DAR0-DAR3)
DMA destination address registers 0-3 (DAR0-DAR3) are 32-bit read/write registers that specify the destination address of a DMA transfer. During a DMA transfer, these registers indicate the next destination address (in single-address mode, DAR is ignored in transfers from memorymapped external devices or external memory to external devices with DACK). The initial value after resets or in standby mode is undefined.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W 23 -- R/W 22 -- R/W 21 -- R/W 20 -- R/W -- R/W ... ... ... ... -- R/W -- R/W -- R/W 0 31 30 29 28 27 26 25 24
174 RENESAS
9.2.3
DMA Transfer Count Registers 0-3 (TCR0-TCR3)
DMA transfer count registers 0-3 (TCR0-TCR3) are 16-bit read/write registers that specify the DMA transfer count (bytes or words). The number of transfers is 1 when the setting is H'0001, 65535 when the setting is H'FFFF and 65536 (the maximum) when H'0000 is set. During a DMA transfer, these registers indicate the remaining transfer count. The initial value after resets or in standby mode is undefined.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W 3 -- R/W 2 -- R/W 1 -- R/W 0 15 14 13 12 11 10 9 8
9.2.4
DMA Channel Control Registers 0-3 (CHCR0-CHCR3)
DMA channel control registers 0-3 (CHCR0-CHCR3) are 16-bit read/write registers that control the DMA transfer mode. They also indicate DMA transfer status. They are initialized to H'0000 by a reset or standby mode.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 DM1 0 R/W 7 AM 0 R/(W)*2 14 DM0 0 R/W 6 AL 0 13 SM1 0 R/W 5 DS 0 12 SM0 0 R/W 4 TM 0 R/W 11 RS3 0 R/W 3 TS 0 R/W 10 RS2 0 R/W 2 IE 0 R/W 9 RS1 0 R/W 1 TE 0 R/(W)* 8 RS0 0 R/W 0 DE 0 R/W
R/(W)*2 R/(W)*2
Notes: 1. Write only 0 to clear the flag. 2. Writing is effective only for CHCR0 and CHCR1.
RENESAS 175
*
Bits 15 and 14 (destination address mode bits 1, 0 (DM1 and DM0)): DM1 and DM0 select whether the DMA destination address is incremented, decremented, or left fixed (in the single address mode, DM1 and DM0 are ignored when transfers are made from memory-mapped external devices or external memory to external devices with DACK). DM1 and DM0 are initialized to 00 by resets or in standby mode.
Bit 14: DM0 0 1 0 1 Description Fixed destination address (initial value) Destination address is incremented (+1 or +2 depending on if the transfer size is word or byte) Destination address is decremented (-1 or -2 depending on if the transfer size is word or byte) Reserved (illegal setting)
Bit 15: DM1 0 0 1 1
*
Bits 13 and 12 (source address mode bits 1, 0 (SM1 and SM0)): SM1 and SM0 select whether the DMA source address is incremented, decremented, or left fixed (in the single address mode, SM1 and SM0 are ignored when transfers are made from external devices with DACK to memory-mapped external devices or external memory). SM1 and SM0 are initialized to 00 by resets or in standby mode.
Bit 12: SM0 0 1 0 1 Description Fixed source address (initial value) Source address is incremented (+1 or +2 depending on if the transfer size is word or byte) Source address is decremented (-1 or -2 depending on if the transfer size is word or byte) Reserved (illegal setting)
Bit 13: SM1 0 0 1 1
*
Bits 11-8 (resource select bits 3-0 (RS3-RS0)): RS3-RS0 specify which transfer requests will be sent to the DMAC. Do not change the transfer request source unless the DMA enable bit (DE) is 0. The RS3-RS0 bits are initialized to 0000 by resets or in standby mode.
176 RENESAS
Bit 11: RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit 10: RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Bit 9: RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Bit 8: RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Description DREQ (External request*1, dual address mode) (initial value) Reserved (illegal setting) DREQ (External request*1, single address mode* 2) DREQ (External request*1, single address mode* 3) RXI0 (On-chip serial communication interface 0 receive data full interrupt transfer request)*4 TXI0 (On-chip serial communication interface 0 transmit data empty interrupt transfer request)*4 RXI1 (On-chip serial communication interface 1 receive data full interrupt transfer request)*4 TXI1 (On-chip serial communication interface 1 transmit data empty interrupt transfer request)*4 IMIA0 (On-chip ITU0 input capture/compare-match A interrupt transfer request)*4 IMIA1 (On-chip ITU1 input capture/compare-match A interrupt transfer request)*4 IMIA2 (On-chip ITU2 input capture/compare-match A interrupt transfer request)*4 IMIA3 (On-chip ITU3 input capture/compare-match A interrupt transfer request)*4 Auto-request (Transfer requests automatically generated within DMAC)*4 Reserved (illegal setting) Reserved (illegal setting) Reserved (illegal setting)
SCI0, SCI1: Serial communications interface channels 0 and 1. ITU0-ITU3: Channels 0-3 of the 16-bit integrated-timer pulse unit. Notes: 1. These bits are valid only in channels 0 and 1. None of these request sources can be selected in channels 2 and 3. 2. Transfer from memory-mapped external device or external memory to external device with DACK. 3. Transfer from external device with DACK to memory-mapped external device or external memory. 4. Dual address mode.
RENESAS 177
*
Bit 7 (acknowledge mode bit (AM)): In the dual address mode, AM selects whether the DACK signal is output during the data read cycle or write cycle. This bit is valid only in channels 0 and 1. The AM bit is initialized to 0 by resets or in standby mode. The AM bit is not valid in single address mode.
Description DACK is output in read cycle (initial value) DACK is output in write cycle
Bit 7: AM 0 1
*
Bit 6 (acknowledge Level Bit (AL)): AL selects active high signal or active low signal for the DACK signal. This bit is valid only in channels 0 and 1. The AL bit is initialized to 0 by resets or in standby mode.
Description DACK is active high (initial value) DACK is active low
Bit 6: AL 0 1
*
Bit 5 (DREQ select bit (DS)): DS selects the DREQ input detection method used. This bit is valid only in channels 0 and 1. The DS bit is initialized to 0 by resets or in standby mode.
Description DREQ detected by low level (initial value) DREQ detected by falling edge
Bit 5: DS 0 1
*
Bit 4 (transfer bus mode bit (TM)): TM selects the bus mode for DMA transfers. The TM bit is initialized to 0 by resets or in standby mode. When the source of the transfer request is an onchip peripheral module, see table 9.4, Selecting On-Chip Peripheral Module Request Modes with the RS Bit.
Description Cycle-steal mode (initial value) Burst mode
Bit 4: TM 0 1
178 RENESAS
*
Bit 3 (transfer size bit (TS)): TS selects the transfer unit size. If the on-chip peripheral module that is the source or destination of the transfer can only be accessed in bytes, byte must be selected in this bit. The TS bit is initialized to 0 by resets or in standby mode.
Description Byte (8 bits) (initial value) Word (16 bits)
Bit 3: TS 0 1
*
Bit 2 (interrupt enable bit (IE)): IE determines whether or not to request a CPU interrupt at the end of a DMA transfer. When the IE bit is set to 1, an interrupt (DEI) is requested from the CPU when the TE bit is set. The IE bit is initialized to 0 by resets or in standby mode.
Description Interrupt request disabled (initial value) Interrupt requeste enabled
Bit 2: IE 0 1
*
Bit 1 (transfer end flag bit (TE)): TE indicates that the transfer has ended. When a DMA transfer ends normally and the value in the DMA transfer count register (TCR) becomes 0, the TE bit is set to 1. This flag is not set if the transfer ends because of an NMI interrupt or address error, or because the DE bit or the DME bit of the DMA operation register (DMAOR) was cleared. To clear the TE bit, read 1 from it and then write 0. When this flag is set, setting the DE bit to 1 does not enable a DMA transfer. The TE bit is initialized to 0 by resets or in standby mode.
Bit 1: TE 0
Description DMA has not ended or was aborted (initial value) To clear TE, the CPU must read TE after it has been set to 1, then write a 0 in this bit
1
DMA has ended normally
RENESAS 179
*
Bit 0 (DMA enable bit (DE)): DE enables or disables DMA transfers. In the auto-request mode, the transfer starts when this bit or the DME bit of the DMAOR is set to 1. The TE bit and the NMIF and AE bits of the DMAOR must be all cleared to 0. In external request mode or on-chip peripheral module request mode, the transfer begins when the DMA transfer request is received from said device or on-chip peripheral module, provided this bit and the DME bit are set to 1. As with the auto request mode, the TE bit and the NMIF and AE bits of the DMAOR must be all cleared to 0. The transfer can be stopped by clearing this bit to 0. The DE bit is initialized to 0 by resets or in standby mode.
Description DMA transfer disabled (initial value) DMA transfer enabled
Bit 0: DE 0 1
9.2.5
DMA Operation Register (DMAOR)
The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMA transfer mode. It also indicates the DMA transfer status. It is initialized to H'0000 by a reset or the standby mode.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 ---- 0 R 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 AE 0 R/(W)* 9 PR1 0 R/W 1 NMIF 0 R/(W)* 8 PR0 0 R/W 0 DME 0 R
Note: Write only 0 to clear the flag.
*
Bits 15-10 (reserved): These bits always read 0. The write value should always be 0.
180 RENESAS
*
Bits 9 and 8 (priority mode bits 1 and 0 (PR1 and PR0)): PR1 and PR0 select the priority level between channels when there are transfer requests for multiple channels simultaneously.
Bit 8: PR0 0 1 0 1 Description Fixed priority order (Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1) (initial value) Fixed priority order (Ch. 1 > Ch. 3 > Ch. 2 > Ch. 0) Round-robin mode priority order (the priority order immediately after a reset is Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1) External-pin round-robin mode priority order (the priority order immediately after a reset is Ch. 3 > Ch. 2 > Ch. 1 > Ch. 0)
Bit 9: PR1 0 0 1 1
* *
Bits 7-3 (reserved): These bits always read 0. The write value should always be 0. Bit 2 (address error flag bit (AE)): AE indicates that an address error occurred in the DMAC. When this flag is set to 1, the channel cannot be enabled even if the DE bit in the DMA channel control register (CHCR) and the DME bit are set to 1. To clear the AE bit, read 1 from it and then write 0. It is initialized to 0 by a reset or the standby mode.
Description No DMAC address error (initial value) To clear the AE bit, read 1 from it and then write 0.
Bit 2: AE 0
1
Address error by DMAC
*
Bit 1 (NMI Flag Bit (NMIF)): NMIF indicates that an NMI interrupt occurred. When this flag is set to 1, the channel cannot be enabled even if the DE bit in the CHCR and the DME bit are set to 1. To clear the NMIF bit, read 1 from it and then write 0. It is initialized to 0 by a reset or the standby mode.
Description No NMI interrupt (initial value) To clear the NMIF bit, read 1 from it and then write 0.
Bit 1: NMIF 0
1
NMI has occurred
RENESAS 181
*
Bit 0 (DMA master enable bit (DME)): DME enables or disables DMA transfers on all channels. A channel becomes enabled for a DMA transfer when the DE bit in each DMA's CHCR and the DME bit are set to 1. For this to be effective, however, the TE bit of each CHCR and the NMIF and AE bits must all be 0. When the DME bit is cleared, all channel DMA transfers are aborted.
Description Disable DMA transfers on all channels (initial value) Enable DMA transfers on all channels
Bit 0: DME 0 1
9.3
Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip module request. Transfer can be in either the single address mode or the dual address mode. The bus mode can be either burst or cycle steal 9.3.1 DMA Transfer Flow
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (TCR), DMA channel control registers (CHCR), and DMA operation register (DMAOR) are set, the DMAC transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0) 2. When a transfer request comes and transfer is enabled, the DMAC transfers 1 transfer unit of data (for an auto-request, the transfer begins automatically when the DE bit and DME bit are set to 1. The TCR value will be decremented by 1). The actual transfer flows vary by address mode and bus mode. 3. When the specified number of transfer have been completed (when TCR reaches 0), the transfer ends normally. If the IE bit of the CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is aborted. Transfers are also aborted when the DE bit of the CHCR or the DME bit of the DMAOR are changed to 0. Figure 9.2 is a flowchart of this procedure.
182 RENESAS
Start
Initial settings (SAR, DAR, TCR, CHCR, DMAOR)
DE, DME = 1 and NMIF, AE, TE = 0? Yes
No
Transfer request occurs?*1 Yes
No
*2 Bus mode, transfer request mode, DREQ detection selection system
*3
Transfer (1 transfer unit); TCR-1 TCR, SAR and DAR updated
TCR = 0? Yes DEI interrupt request (when IE = 1) Does NMIF = 1, AE = 1, DE = 0, and DME = 0? Yes Transfer ends
No
Does NMIF = 1, AE = 1, DE = 0, or DME = 0? Yes Transfer aborted
No
No
Normal end Notes: 1. 2. 3.
In auto-request mode, transfer begins when NMIF, AE and TE are all and the DE and DME bits are set to 1. DREQ = level detection in the burst mode (external request), or cycle steal mode. DREQ = edge detection in the burst mode (external request), or auto request mode in burst mode.
Figure 9.2 DMA Transfer Flowchart
RENESAS 183
9.3.2
DMA Transfer Requests
DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip module request. The request mode is selected in the RS3-RS0 bits of the DMA channel control registers 0-3 (CHCR0-CHCR3). Auto-Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits of CHCR0-CHCR3 and the DME bit of the DMAOR are set to 1, the transfer begins (so long as the TE bits of CHCR0-CHCR3 and the NMIF and AE bits of DMAOR are all 0). External Request Mode: In this mode a transfer is performed at the request signal (DREQ) of an external device. Choose one of the modes shown in table 9.3 according to the application system. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon a request at the DREQ input. Choose to detect DREQ by either the falling edge or low level of the signal input with the DS bit of CHCR0-CHCR3 (DS = 0 is level detection, DS = 1 is edge detection). The source of the transfer request does not have to be the data transfer source or destination. Table 9.3
RS3 0 0 RS2 0 0
Selecting External Request Modes with the RS Bits
RS1 0 1 RS0 0 0 Address Mode Dual address mode Single address mode Single address mode Source Any* External memory or memory-mapped external device External device with DACK Destination Any* External device with DACK External memory or memory-mapped external device
0
0
1
1
Note: External memory, memory-mapped external device, on-chip memory, on-chip peripheral module (excluding DMAC)
On-Chip Module Request: In this mode a transfer is performed at the transfer request signal (interrupt request signal) of an on-chip module. The transfer request signals include the receive data full interrupt (RXI) of the serial communication interface (SCI), the transmit data empty interrupt (TXI) of the SCI, the input capture A/compare match A interrupt request (IMIA) of the 16-bit integrated-pulse timer (ITU), (table 9.4). When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request signal. The source of the transfer request does not have to be the data transfer
184 RENESAS
source or destination. When RXI is set as the transfer request, however, the transfer source must be the SCI's receive data register (RDR). Likewise, when TXI is set as the transfer request, the transfer source must be the SCI's transmit data register (TDR). Table 9.4 Selecting On-Chip Peripheral Module Request Modes with the RS Bit
DMA Transfer Request DMA Transfer Request RS3 RS2 RS1 RS0 Source Signal 0 0 1 1 0 0 0 1 SCI0 receiver SCI0 transmitter SCI1 receiver SCI1 transmitter ITU0 ITU1 ITU2 ITU3 RXI0 (SCI0 receive data full interrupt transfer request) TXI0 (SCI0 transmit data empty interrupt transfer request) RXI1 (SCI1 receive data full interrupt transfer request) TXI1 (SCI1 transmit data empty interrupt transfer request) IMIA0 (ITU0 input capture A/ compare-match A) IMIA1 (ITU1 input capture A/ compare-match A) IMIA2 (ITU2 input capture A/ compare-match A) IMIA3 (ITU3 input capture A/ compare-match A)
Source RDR0 Any
Desti- Bus Mode nation Any* TDR0 Cycle steal Cycle steal
0 0
1 1
1 1
0 1
RDR1 Any*
Any* TDR1
Cycle steal Cycle steal
1 1 1 1
0 0 0 0
0 0 1 1
0 1 0 1
Any* Any* Any* Any*
Any* Any* Any* Any*
Burst/Cycle steal Burst/Cycle steal Burst/Cycle steal Burst/Cycle steal
SCI0, SCI1: Serial communications interface channels 0 and 1 ITU0-ITU3: Channels 0-3 of the 16-bit integrated-timer pulse unit. RDR0, RDR1: Receive data registers 0, 1 of SCI TDR0, TDR1: Transmit data registers 0, 1 of SCI Note: External memory, memory-mapped external device, on-chip memory, on-chip peripheral module (excluding DMAC)
When outputting transfer requests from on-chip peripheral modules, the appropriate interrupt enable bits must be set to output the interrupt signals. Note that transfer request signals from onchip peripheral modules (interrupt request signals) are sent not just to the DMAC but to the CPU as well. When an on-chip peripheral module is specified as the transfer request source, set the priority level values in the interrupt priority level registers (IPRC-IPRE) of the interrupt controller (INTC) at or below the levels set in the I3-I0 bits of the CPU's status register (SR) so that the CPU does not acknowledge the interrupt request signal.
RENESAS 185
The DMA transfer request signals of table 9.4 are automatically withdrawn when the corresponding DMA transfer is performed. If the cycle steal mode is being employed, the DMA transfer request (interrupt request) will be cleared at the first transfer; if the burst mode is being used, it will be cleared at the last transfer. 9.3.3 Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. The three modes (fixed mode, round-robin mode, and external-pin round-robin mode) are selected by the priority bits PR1 and PR0 in the DMA operation register. Fixed Mode: In these modes, the priority levels among the channels remain fixed. When PR1 and PR0 bits are set 00, the priority order, high to low, is Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1. When PR1 and PR0 bits are set 01, the priority order, high to low, is Ch. 1 > Ch. 3 > Ch. 2 > Ch. 0. Round-Robin Mode: Each time one word or byte is transferred on one channel, the priority order is rotated. The channel on which the transfer was just finished rotates to the bottom of the priority order. When necessary, the priority order of channels other than the one that just finished the transfer can also be shifted to keep the relationship between the channels from changing (figure 9.3). The priority order immediately after a reset is channel 0 > channel 3 > channel 2 > channel 1.
186 RENESAS
(1) When channel 0 transfers Initial priority order ch0 > ch3 > ch2 > ch1 Channel 0 becomes bottom priority ch3 > ch2 > ch1 > ch0
Priority order after transfer
(2) When channel 3 transfers Initial priority order ch0 > ch3 > ch2 > ch1 Channel 3 becomes bottom priority. The priority of channel 0, which was higher than channel 3, is also shifted.
Priority order after transfer
ch2 > ch1 > ch0 > ch3
(3) When channel 2 transfers Initial priority order ch0 > ch3 > ch2 > ch1
Priority order after transfer
ch1 > ch0 > ch3 > ch2
Post-transfer priority order when there is an immediate transfer request to channel 3 only
ch2 > ch1 > ch0 > ch3
Channel 2 becomes bottom priority. The priority of channels 0and 3, which were higher than channel 2, are also shifted. If immediately thereafter there is a request to transfer channel 3 only, channel 3 becomes bottom priority and the priority of channels 0 and 1, which were higher than channel 3, are also shifted.
(4) When channel 1 transfers Initial priority order ch0 > ch3 > ch2 > ch1 Priority order does not change Priority order after transfer ch0 > ch3 > ch2 > ch1
Figure 9.3 Round-Robin Mode Figure 9.4 shows how the priority order changes when channel 0 and channel 1 transfers are requested simultaneously and a channel 3 transfer is requested during the channel 0 transfer. The DMAC operates as follows:
RENESAS 187
1. Transfer requests are generated simultaneously to channels 1 and 0. 2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 1 waits for transfer). 3. A channel 3 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. When the channel 0 transfer ends, channel 0 becomes lowest priority. 5. At this point, channel 3 has a higher priority than channel 1, so the channel 3 transfer begins (channel 1 waits for transfer). 6. When the channel 3 transfer ends, channel 3 becomes lowest priority. 7. The channel 1 transfer begins. 8. When the channel 1 transfer ends, channels 1 and 2 shift downward in priority so that channel 1 becomes the lowest priority.
Transfer request
Waiting channel(s)
DMAC operation (2) Channel 0 transfer starts
Channel priority
(1) Channels 0 and 1
0>3>2>1
1 (3) Channel 3
1, 3
(4) Channel 0 transfer ends (5) Channel 3 transfer starts
Priority order changes
3>2>1>0
1
(6) Channel 3 transfer ends (7) Channel 1 transfer starts
Priority order changes
2>1>0>3
None (8) Channel 1 transfer ends
Priority order changes
0>3>2>1
Figure 9.4 Changes in Channel Priority in Round-Robin Mode
188 RENESAS
External-Pin Round-Robin Mode: External-pin round-robin mode switches the priority levels of channel 0 and channel 1, which are the channels that can receive transfer requests from external pins DREQ0 and DREQ1. The priority levels are changed after each (byte or word) transfer on channel 0 or channel 1 is completed. The channel which just finished the transfer rotates to the bottom of the priority order. The priority levels of channels 2 and 3 do not change. The initial priority order after a reset is channel 3 > channel 2 > channel 1 > channel 0. Figure 9.5 shows how the priority order changes when channel 0 and channel 1 transfers are requested simultaneously and a channel 0 transfer is requested again after both channels finish their transfers. The DMAC operates as follows: 1. Transfer requests are generated simultaneously to channels 1 and 0. 2. Channel 1 has a higher priority, so the channel 1 transfer begins first (channel 0 waits for transfer). 3. When the channel 1 transfer ends, channel 1 becomes lowest priority. 4. The channel 0 transfer begins. 5. When the channel 0 transfer ends, channel 0 becomes lowest priority. 6. A channel 0 transfer request occurs again. 7. The channel 0 transfer begins. 8. When the channel 0 transfer ends, the priority order does not change, because channel 0 is already the lowest priority.
RENESAS 189
Transfer request (1) Channels 0 and 1
Waiting channel(s)
DMAC operation (2) Channel 1 transfer starts
Channel priority
3>2>1>0 Priority order changes
0 (3) Channel 1 transfer ends
3>2>0>1
(4) Channel 0 transfer starts None (5) Channel 0 transfer ends Priority order changes
3>2>1>0
(6) Channel 0
(7) Channel 0 transfer starts None (8) Channel 0 transfer ends
Waiting for transfer request
Priority order does not change
3>2>1>0
Figure 9.5 Example of Changes in Priority in External-Pin Round-Robin Mode
190 RENESAS
9.3.4
DMA Transfer Types
The DMAC supports the transfers shown in table 9.5. It can operate in the single address mode or dual address mode, which are defined by how many bus cycles the DMAC takes to access the transfer source and transfer destination. The actual transfer operation timing varies with the bus mode. The DMAC has two bus modes: cycle-steal mode and burst mode. Table 9.5 Supported DMA Transfers
Destination External Device with DACK MemoryMapped External On-Chip Device Memory Single Dual Dual Dual Dual Not available Dual Dual Dual Dual On-Chip Peripheral Module Not available Dual Dual Dual Dual
Source
External Memory Single Dual Dual Dual Dual
External device with DACK Not available External memory Single
Memory-mapped external Single device On-chip memory Not available
On-chip peripheral module Not available Single: Single address mode Dual: Dual address mode
RENESAS 191
Address Modes: * Single Address Mode In the single address mode, both the transfer source and destination are external; one (selectable) is accessed by a DACK signal while the other is accessed by an address. In this mode, the DMAC performs the DMA transfer in 1 bus cycle by simultaneously outputting a transfer request acknowledge DACK signal to one external device to access it while outputting an address to the other end of the transfer. Figure 9.6 shows an example of a transfer between an external memory and an external device with DACK in which the external device outputs data to the data bus while that data is written in external memory in the same bus cycle.
External address bus External data bus SH microcomputer DMAC Read Write * *
(1) (2)
External memory
External device with DACK
DACK DREQ : Data flow Note: The read/write direction is decided by the RS3-RS0 bits of the CHCRn registers. If RS3RS0=0010, the direction is shown as case 1 (circled number above); if RS3-RS0=0010, the direction is shown as case 2. Also, DACK output (when writing) indicates case 2.
Figure 9.6 Data Flow in Single Address Mode Two types of transfers are possible in the single address mode: 1) transfers between external devices with DACK and memory-mapped external devices, and 2) transfers between external devices with DACK and external memory. The only transfer requests for either of these is the external request (DREQ). Figure 9.7 shows the DMA transfer timing for the single address mode.
192 RENESAS
The DACK output when a transfer occurs from an external device with DACK to a memorymapped external device is the write waveform. The DACK output when a transfer occurs from a memory-mapped external device to an external device with DACK is the read waveform. The setting of the acknowledge mode (AM) bits in the channel control registers (CHCR0, CHCR1) have no effect.
CK A21-A0 CSn D15-D0 DACK WRH WRL Data that is output from the external device with DACK DACK signal to external devices with DACK (active low) WR signal to external memory space (a) External device with DACK to external memory space Address output to external memory space
CK A21-A0 CSn D15-D0 RD DACK Data that is output from external memory space RD signal to external memory space DACK signal to external device with DACK (active low) (b) External memory space to external device with DACK Address output to external memory space
Figure 9.7 Example of DMA Transfer Timing in the Single Address Mode
RENESAS 193
*
Dual Address Mode In the dual address mode, both the transfer source and destination are accessed (selectable) by an address. The source and destination can be located externally or internally. The source is accessed in the read cycle and the destination in the write cycle, so the transfer is performed in two separate bus cycles. The transfer data is temporarily stored in the DMAC. Figure 9.8 shows an example of a transfer between two external memories in which data is read from one memory in the read cycle and written to the other memory in the following write cycle.
External data bus SuperH microcomputer DMAC 2
External memory
External memory 1
: Data flow 1: Read cycle 2: Write cycle
Figure 9.8 Data Flow in Dual Address Mode In the dual address mode transfers, external memory, memory-mapped external devices, onchip memory and on-chip peripheral modules can be mixed without restriction. Specifically, this enables the following transfer types: External memory and external memory transfer External memory and memory-mapped external devices transfer Memory-mapped external devices and memory-mapped external devices transfer External memory and on-chip memory transfer External memory and on-chip peripheral modules (excluding the DMAC) transfer Memory-mapped external devices and on-chip memory transfer Memory-mapped external devices and on-chip peripheral modules (excluding the DMAC) transfer 8. On-chip memory and on-chip memory transfer 9. On-chip memory and on-chip peripheral modules (excluding the DMAC) transfer 10. On-chip peripheral modules (excluding the DMAC) and on-chip peripheral modules (excluding the DMAC) transfer
194 RENESAS
1. 2. 3. 4. 5. 6. 7.
Transfer requests can be auto requests, external requests, or on-chip peripheral module requests. When the transfer request source is either the SCI or A/D converter, however, either the data destination or source must be the SCI or A/D converter (figure 9.4), In dual address mode, DACK is output in read or write cycles to onchip memory or onchip peripheral modules. The CHCR controls the cycle of DACK output. Figure 9.9 shows the DMA transfer timing in the dual address mode.
CK A21-A0 Source address CSn D15-D0 RD WRH WRL DACK Destination address
Figure 9.9 DMA Transfer Timing in the Dual Address Mode (External memory space to external memory space transfer with DACK output in the read cycle) Bus Modes: There are two bus modes: cycle steal and burst. Select the mode in the TM bits of CHCR0-CHCR3. * Cycle-Steal Mode In the cycle steal mode, the bus right is given to another bus master after a one-transfer-unit (word or byte) DMA transfer. When another transfer request occurs, the bus rights are obtained from the other bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus right is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. The cycle steal mode can be used with all categories of transfer destination, transfer source and transfer request. Figure 9.10 shows an example of DMA transfer timing in the cycle steal mode. Transfer conditions shown in the figure are: Dual address mode DREQ level detection
RENESAS 195
DREQ Bus right returned to CPU Bus cycle CPU CPU CPU DMAC DMAC Read Write CPU DMAC Read DMAC Write CPU
Figure 9.10 Transfer Example in the Cycle-Steal Mode (Dual address mode, DREQ level detection) * Burst Mode Once the bus right is obtained, the transfer is performed continuously until the transfer end condition is satisfied. In the external request mode with low level detection of the DREQ pin, however, when the DREQ pin is driven high, the bus passes to the other bus master after the bus cycle of the DMAC that currently has an acknowledged request ends, even if the transfer end conditions have not been satisfied. The burst mode cannot be used when the serial communications interface (SCI) is the transfer request source. Figure 9.11 shows an example of DMA transfer timing in the burst mode. The transfer conditions shown in the figure are: Single address mode DREQ level detection
DREQ
Bus cycle
CPU
CPU
CPU
DMAC DMAC DMAC DMAC DMAC DMAC
CPU
Figure 9.11 Transfer Example in the Burst Mode (Single address mode, DREQ level detection) Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 9.6 shows the relationship between request modes and bus modes by DMA transfer category.
196 RENESAS
Table 9.6
Relationship of Request Modes and Bus Modes by DMA Transfer Category
Request Mode External External Everything*1 Everything*1 Bus Mode B/C B/C B/C B/C B/C B/C B/C* 3 B/C B/C* 3 B/C B/C* 3 B/C* 3 Transfer Size (bits) 8/16 8/16 8/16 8/16 8/16 8/16 8/16*4 8/16 8/16*4 8/16 8/16*4 8/16*4 Usable Channels 0,1 0, 1 0-3* 5 0-3* 5 0-3* 5 0-3* 5 0-3* 5 0-3* 5 0-3* 5 0-3* 5 0-3* 5 0-3* 5
Addres s Mode Transfer Category Single External device with DACK and external memory External device with DACK and memory-mapped external device Dual External memory and external memory External memory and memorymapped external device
Memory-mapped external device and Everything*1 memory-mapped external device External memory and on-chip memory External memory and on-chip peripheral module Everything*1 Everything*2
Memory-mapped external device and Everything*1 on-chip memory Memory-mapped external device and Everything*2 on-chip peripheral module On-chip memory and on-chip memory On-chip memory and on-chip peripheral module On-chip peripheral module and onchip peripheral module Everything*1 Everything*2 Everything*2
B: Burst, C: Cycle steal Notes: 1. External requests, auto requests and on-chip peripheral module requests are all available. For on-chip peripheral module requests, however, SCI cannot be specified as the transfer request source. 2. External requests, auto requests and on-chip peripheral module requests are all available. When the SCI is also the transfer request source, however, the transfer destination or transfer source must be the SCI respectively. 3. If the transfer request source is the SCI, cycle steal only. 4. The access size permitted when the transfer destination or source is an on-chip peripheral module register. 5. If the transfer request is an external request, channels 0 and 1 only.
Bus Mode and Channel Priority Order: When a given channel (1) is transferring in burst mode and there is a transfer request to a channel (2) with a higher priority, the transfer of the channel
RENESAS 197
with higher priority (2) will begin immediately. When channel 2 is also operating in the burst mode, the channel 1 transfer will continue when the channel 2 transfer has completely finished. When channel 2 is in the cycle steal mode, channel 1 will begin operating again after channel 2 completes the transfer of one transfer unit, but the bus will then switch between the two in the order channel 1, channel 2, channel 1, channel 2. Since channel 1 is in burst mode, it will not give the bus to the CPU. This example is illustrated in figure 9.12.
Bus status
CPU
DMAC ch1
DMAC ch1
DMAC ch2
DMAC ch1
DMAC ch2
DMAC ch1
DMAC ch1
CPU
ch2 DMAC ch1 Burst mode
ch1
ch2 DMAC ch1 Burst mode
CPU
DMAC ch1 and ch2 Cycle steal mode
CPU
Figure 9.12 Bus Handling when Multiple Channels Are Operating 9.3.5 Number of Bus Cycle States and DREQ Pin Sample Timing
Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the bus master is controlled by the bus state controller just as it is when the CPU is the bus master. The bus cycle in the dual address mode is controlled by wait state control register 1 (WCR1) while the single address mode bus cycle is controlled by wait state control register 2 (WCR2). For details, see section 8.9, Wait State Control. DREQ Pin Sampling Timing: Normally, when DREQ input is detected immediately prior to the rise edge of the clock pulse (CK) in external request mode, a DMAC bus cycle will be generated and the DMA transfer performed two states later at the earliest. The sampling timing after DREQ input detection differs by bus mode, address mode and method of DREQ input detection. * DREQ pin sampling timing in the cycle steal mode In the cycle steal mode, the sampling timing is the same regardless of whether the DREQ is detected by edge or level. When edge is being detected, however, once sampled it will not be sampled again until the next edge detection. Once DREQ input is detected, the next sampling is not performed until the first state, among those DMAC bus cycles thereby produced, in which a DACK signal is output (including the detection state itself). The next sampling occurs immediately prior to the rise edge of the clock pulse(CK) of the third state after the bus cycle previous to the bus cycle in which the DACK signal is output.
198 RENESAS
Figure 9.13 to 9.22 show the sampling timing of the pin DREQ in the cycle steal mode for each bus cycle. When no DREQ input is detected at the sampling after the aforementioned DREQ detection, the next sampling occurs in the next stage in which a DACK signal is output. If no DREQ input is detected at this time, sampling occurs at every state thereafter.
CK
DREQ
Bus cycle
CPU
CPU
CPU
DMAC
CPU
CPU
CPU
CPU
DACK
Figure 9.13 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Single address mode, bus cycle = 1 state)
CK
DREQ
Bus cycle
CPU
CPU
CPU
DMAC (R) DMAC (W)
CPU
CPU
CPU
DACK DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle
Note:
Illustrates the case when DACK is output during the DMAC Read cycle.
Figure 9.14 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Dual address mode, bus cycle = 1 state)
RENESAS 199
CK
DREQ
Bus cycle
CPU
CPU
CPU
DMAC
CPU
CPU
CPU
CPU
DACK
Figure 9.15 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Single address mode, bus cycle = 2 states)
CK
DREQ
Bus cycle
CPU
CPU
CPU
DMAC (R) DMAC (W)
CPU
CPU
CPU
DACK
DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle
Note:
Illustrates the case when DACK is output during the DMAC write cycle.
Figure 9.16 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Dual address mode, bus cycle = 2 states)
200 RENESAS
T1 Tw T2
T1 Tw T2
CK
DREQ
Bus cycle
CPU
CPU
CPU
DMAC
CPU
DMAC
CPU
DACK
Note:
When DREQ is negated at the third state of the DMAC cycle, the next DMA transfer will be executed because the sampling is done at the second state of the DMAC cycle.
Figure 9.17 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Single address mode, bus cycle = 2 states + 1 wait state)
T1 Tw T2 T1 Tw T2
CK
DREQ
Bus cycle
CPU
CPU
CPU
DMAC (R)
DMAC (W)
CPU
CPU
DACK
DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle
Figure 9.18 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Dual address mode, bus cycle = 2 states + 1 wait state)
RENESAS 201
Tp Tr Tc Tc CK
Tp Tr Tc Tc
DREQ
Bus cycle
CPU
CPU
CPU
DMAC
CPU
DMAC
CPU
DACK
Note:
When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will be executed because the sampling is done at the second state of the DMAC cycle.
Figure 9.19 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Single address mode, bus cycle = DRAM bus cycle (long pitch normal mode))
Tp Tr Tc Tc CK
Tp Tr Tc Tc
DREQ
Bus cycle
CPU CPU CPU
DMAC(R)
DMAC (W)
CPU
DMAC (R)
DMAC (W)
CPU
DACK
DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle
Note:
When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will be executed because the sampling is done at the second state of the DMAC cycle.
Figure 9.20 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Dual address mode, bus cycle = DRAM bus cycle (long pitch normal mode))
202 RENESAS
T1 T2 T3 T4 CK
T1 T2 T3 T4
DREQ
Bus cycle
CPU
CPU
CPU
DMAC
CPU
DMAC
CPU
DACK
Note:
When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will be executed because the sampling is done at the second state of the DMAC cycle.
Figure 9.21 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Single address mode, bus cycle = Address/data multiplex I/O bus cycle)
T1 T2 T3 T4 CK
T1 T2 T3 T4
DREQ
Bus cycle
CPU CPU CPU
DMAC(R)
DMAC (W)
CPU
DMAC (R)
DMAC (W)
CPU
DACK
DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will be executed because the sampling is done at the second state of the DMAC cycle.
Figure 9.22 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Dual address mode, bus cycle = Address/data multiplex I/O bus cycle)
RENESAS 203
*
DREQ pin sampling timing in the burst mode In the burst mode, the sampling timing differs depending on whether DREQ is detected by edge or level. When DREQ input is being detected by edge, once the falling edge of the DREQ signal is detected, the DMA transfer continues until the transfer end conditions are satisfied, regardless of the status of the DREQ pin. No sampling happens during this time. After the transfer ends, sampling occurs every state until the TE bit of the CHCR is cleared. When DREQ input is being detected by level, once the DREQ input is detected, next sampling is performed at the end of every CPU or DMAC bus cycle in the single address mode. In the dual address mode, the next sampling is performed at the start of every DMAC read cycle. In both the single address mode and dual address mode, if no DREQ input is detected at this time, sampling thereafter occurs at every state. Figures 9.23 and 9.24 show the DREQ pin sampling timing in burst mode when DREQ input is detected by low level.
CK
DREQ
Bus cycle
CPU
CPU
CPU
DMAC
DMAC
DMAC
CPU
DACK
Note: Single address DREQ level detection, DACK active low, 1 bus cycle = 2 states.
Figure 9.23 DREQ Pin Sampling Timing in Burst Mode
204 RENESAS
CK
DREQ
Bus cycle
CPU
CPU
DMAC(R)
DMAC(W)
DMAC(R)
DMAC(W)
CPU
DACK
Note:
Dual address DREQ level detection, DACK active low, DACK output in read cycle, 1 bus cycle = 2 states.
Figure 9.24 DREQ Pin Sampling Timing in Burst Mode 9.3.6 DMA Transfer Ending Conditions
The DMA transfer ending conditions vary for individual channels ending and all channels ending together. Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when the value of the channel's DMA transfer count register (TCR) is 0, or when the DE bit of the channel's CHCR is cleared to 0. * When TCR is 0: When the TCR value becomes 0 and the corresponding channel's DMA transfer ends, the transfer end flag bit (TE) is set in the CHCR. If the IE (interrupt enable) bit has been set, a DMAC interrupt (DEI) is requested to the CPU. When DE of CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the channel's CHCR. The TE bit is not set when this happens.
*
Conditions for Ending All Channels Simultaneously: Transfers on all channels end when 1) the NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in the DMAOR, or 2) when the DME bit in the DMAOR is cleared to 0.
RENESAS 205
*
*
Transfers ending when the NMIF or AE bit is set to 1 in DMAOR: When an NMI interrupt or DMAC address error occurs, the NMIF or AE bit is set to 1 in the DMAOR and all channels stop their transfers. The SAR, DAR, TCR are all updated by the transfer immediately preceding the halt. The TE bit is not set. To resume the transfers after NMI interrupt exception processing or address error exception processing, clear the appropriate flag bit to 0. When a channel's DE bit is then set to 1, the transfer on that channel will restart. To avoid restarting a transfer on a particular channel, keep its DE bit cleared to 0. In the dual address mode, the DMA transfer will be halted after the completion of the write cycle that follows the initial read cycle in which the address error occurs. SAR, DAR and TCR are updated by the final transfer. Transfers ending when DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in the DMAOR forcibly aborts the transfers on all channels at the end of the current cycle. The TE bit is not set.
9.4
9.4.1
Examples of Use
DMA Transfer between On-Chip RAM and a Memory-Mapped External Device
In the following example, data is transferred from an on-chip RAM to a memory-mapped external device with an input capture A/compare match A interrupt (IMIA0) from channel 0 of the 16-bit integrated-timer pulse unit (ITU) as the transfer request signal. The transfer is performed by DMAC channel 3. Table 9.7 shows the transfer conditions and register values. Table 9.7 Transfer Conditions and Register Settings for Transfer Between On-Chip RAM and Memory-Mapped External Device
Register SAR3 DAR3 TCR3 CHCR3 Setting H'FFFFE00 Destination address H'0008 H'1805
Transfer Conditions Transfer source: on-chip RAM Transfer destination: memory-mapped external device Number of transfers: 8 Transfer destination address: fixed Transfer source address: incremented Transfer request source (transfer request signal): ITU channel 0 (IMIA0) Bus mode: cycle steal Transfer unit: byte DEI interrupt request generated at end of transfer (channel 3 enabled for transfer) Channel priority order: fixed (0 > 3 > 2 > 1) (all channels transfer enabled)
DMAOR
H'0001
206 RENESAS
9.4.2
Example of DMA Transfer between On-Chip SCI and External Memory
In this example, receive data of on-chip serial communications interface (SCI) channel 0 is transferred to external memory using DMAC channel 3. Table 9.8 shows the transfer conditions and register settings. Table 9.8 Transfer Conditions and Register Settings for Transfer between On-Chip SCI and External Memory
Register SAR3 DAR3 TCR3 CHCR3 Setting H'FFFFEC5 Destination address H'0040 H'4405
Transfer Conditions Transfer source: RDR0 of on-chip SCI0 Transfer destination: external memory Number of transfers: 64 Transfer destination address: incremented Transfer source address: fixed Transfer request source (transfer request signal): SCI0 (RXI0) Bus mode: cycle steal Transfer unit: byte DEI interrupt request generated at end of transfer (channel 3 enabled for transfer Channel priority order: fixed (0 > 3 > 2 > 1) (all channels transfer enabled)
DMAOR
H'0001
RENESAS 207
9.5
Cautions
1. All registers other than the DMA operations register (DMAOR) and DMA channel control registers 0-3 (CHCR0-CHCR3) should be accessed in word or long word units. 2. Before rewriting the RS0-RS3 bits of CHCR0-CHCR3, first clear the DE bit to 0 (when rewriting CHCR with a byte access, be sure to set the DE bit to 0 in advance). 3. Even when the NMI interrupt is input when the DMAC is not operating, the NMIF bit of the DMAOR will be set. 4. Interrupt during DMAC Transfer a. When an NMI interrupt is input, the DMAC stops operation and returns the bus right to the CPU. The CPU then executes the interrupt processing. b. When an interrupt other than an NMI occurs. * When the DMAC is in burst mode. The DMAC does not return the bus right to the CPU in burst mode. Therefore, even when an interrupt is requested in DMAC operation, the CPU cannot get the bus right, causing the interrupt processing not to be executed. When the DMAC completes transfer and the CPU gets the bus right, the CPU executes the interrupt processing if the interrupt requested during DMAC transfer is not cleared.* * Clear conditions for an interrupt request. When an interrupt is requested from an on-chip peripheral module, the interrupt factor flag is cleared. When an interrupt is requested by IRQ (edge detection), the CPU begins the IRQ interrupt processing of the request source. When an interrupt is requested by IRQ (level detection), the IRQ interrupt request signal returned to high level. * When the DMAC is in cycle-steal mode. The DMAC returns the bus right to the CPU every when the DMAC completes a transfer unit in cycle-steal mode. Therefore, the CPU executes the requested interrupt processing when getting the bus right. 5. The CPU and DMAC leaves the bus right released and the operation of the LSI is stopped when the following conditions are satisfied. * The warp bit (WARP) of the bus control register (BCR) of the bus controller (BSC)is set. * The DMAC is in cycle-steal transfer mode. * The CPU accesses (reads/writes) the on-chip I/O space. * Countermeasure Set the warp bit of BCR to 0 and set it to normal mode.
208 RENESAS
6. Notes on use of the SLEEP command a. Operation contents When the bus cycle of DMAC is entered immediately after executing the SLEEP command, there are cases when the DMA transfer is carried out correctly. b. Countermeasure * Stop the operation (for exemple, clearing of the DMA enable bit (DE) of the DMA channel control register(CHCRn)) before entering SLEEP. * When using DMAC during SLEEP, operate DMAC after releasing SLEEP through interruption. In cases when the CPU does not carry out any other processing but is waiting for DMAC to end its transfer during DMAC operation, do not use the SLEEP command, but use the transfer end flag bit (TE) of the channel DMA control register and the polling software loop. Phenomenon: If the bus cycle of DMAC is entered immediately after executing the SLEEP command, the bus cycle of DMAC may conflict with that of CPU.
Address bus
CPU
CPU
CPU
DMAC CPU
DMAC
CPU
Fetch cycle of SLEEP command
This is in itself a DMAC cycle but involves CPU operation.
Accordingly, the bus cycle of DMAC which has conflicted with that of CPU may malfunction. 7. Sampling of DREQ If DREQ is set to level detection in the DMA cycle steal mode, sampling of DREQ may take place before DACK is output. Note that some system configurations involve unnecessary DMA transfers. * Operation As shown in Figure 9.16, sampling of DREQ is carried out immediately before the leading edge of the third-state clock (CK) after completion of the bus cycle preceding the DMA bus cycle where DACK is output. If DACK is output after the third state of the DMA bus cycle, sampling of DREQ must be carried out before DACK is output.
RENESAS 209
Number of states of DMAC bus cycle 1 2 3 4 : Bus cycle of DMAC Sampling point
Figure 9.16 Sampling Points of DREQ Especially as shown in Figure 9.17, if the bus cycle of DMA is a full access to DRAM or if refresh demand is generated, sampling of DREQ takes place before DACK is output as mentioned above. This phenomenon is found when one of the following transfers is made with DREQ set to the level detection in the DMA cycle steal mode, in a system which employs DRAM (refresh enabled).
CK Tp DACK Tr Tc Refresh T1 T2
Sampling point Bus cycle of DRAM (Full access)
Sampling point When refresh operation is entered Sampling point of DREQ for DACK output position differs with presence/absence of the refresh operation.
Figure 9.17 Example of DREQ Sampling before Output of DACK * Transfer from a device having DACK to memory in the single address mode (not restricted to DRAM) * Transfer from DRAM to a device having DACK in the single address mode * Output at DACK write in the dual address mode Output at DACK read in the dual address mode and DMA transfer using DRAM as a source * Countermeasure To prevent unnecessary DMA transfers, configure the system where DREQ is used for edge detection and the edge corresponding to the next transfer request occurs after the DACK output.
210 RENESAS
8. When the following operations are performed in the order shown when the pin to which DREQ input is assigned is designated as a general input pin by the pin function controller (PFC) and inputs a low-level signal, the DREQ falling edge is detected, and a DMA transfer request accepted, immediately after the setting in (b) is performed: (a) A channel control register (CHCRn) setting is made so that an interrupt is detected at the falling edge of DREQ. (b) The function of the pin to which DREQ input is assigned is switched from general input to DREQ input by a pin function controller (PFC) setting. Therefore, when switching the pin function from general input pin to DREQ input, the pin function controller (PFC) setting should be changed to DREQ input while the pin to which DREQ input is assigned is high.
RENESAS 211
Section 10 16-Bit Integrated-Timer Pulse Unit (ITU)
10.1 Overview
The SuperH microcomputer has an on-chip 16-bit integrated-timer pulse unit (ITU) with five channels of 16-bit timers. 10.1.1 Features
ITU features are listed below: * * * Can process a maximum of twelve different pulse outputs and ten different pulse inputs. Has ten general registers (GR), two per channel, that can be set to function independently as output compare or input capture. Selection of eight counter input clock sources for all channels Internal clock: , /2, /4, /8, External clock: TCLKA, TCLKB, TCLKC, TCLKD All channels can be set for the following operating modes: Compare match waveform output: 0 output/1 output/selectable toggle output (0 output/1 output for channel 2). Input capture function: Selectable rising edge, falling edge, or both rising and falling edges. Counter clearing function: Counters can be cleared by a compare match or input capture. Synchronizing mode: Two or more timer counters (TCNT) can be written to simultaneously. Two or more timer counters can be simultaneously cleared by a compare match or input capture. Counter synchronization functions enable synchronized input/output. PWM mode: PWM output can be provided with any duty cycle. When combined with the counter synchronizing function, enables up to five-phase PWM output. Channel 2 can be set to the phase counting mode: Two-phase encoder output can be counted automatically. Channels 3 and 4 can be set in the following modes: Reset-synchronized PWM mode: By combining channels 3 and 4, 3-phase PWM output is possible with positive and negative waveforms . Complementary PWM mode: By combining channels 3 and 4, 3-phase PWM output is possible with non-overlapping positive and negative waveforms. Buffer operation: Input capture registers can be double-buffered. Output compare registers can be updated automatically. High-speed access via internal 16-bit bus: The TCNT, GR, and buffer register (BR) 16-bit registers can be accessed at high speed via a 16-bit bus.
RENESAS 213
*
* *
* *
* * *
Fifteen interrupt sources: Ten compare match/input capture interrupts (2 sources per channel) and five overflow interrupts are vectored independently for a total of 15 sources. Can activate DMAC: The compare match/input capture interrupts of channels 0-3 can start the DMAC (one for each of four channels). Output trigger can be generated for the programmable timing pattern controller (TPC): The compare match/input capture signals of channel 0-3 can be used as output triggers for the TPC.
Table 10.1 summarizes the ITU functions.
214 RENESAS
Table 10.1 ITU Functions
Item Counter clocks General registers (output compare/ input capture dual registers) Buffer registers Input/output pins Output pins Channel 0 Channel 1 Channel 2 Channel 3 Channel 4
Internal: , /2, /4, /8 External: Independently selectable from TCLKA, TCLKB, TCLKC, and TCLKD GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 GRA4, GRB4
No TIOCA0, TIOCB0 No
No TIOCA1, TIOCB1 No GRA1/GRB1
No TIOCA2, TIOCB2 No GRA2/GRB2
BRA3, BRB3 TIOCA3, TIOCB3 No GRA3/GRB3
BRA4, BRB4 TIOCA4, TIOCB4 TOCXA4, TOCXB4 GRA4/GRB4
Counter clear func- GRA0/GRB0 tion (compare match or input capture) Compare 0 Yes match 1 Yes output Toggle Yes output Input capture function Synchronization PWM mode Yes Yes Yes
Yes Yes Yes Yes Yes Yes No No No No
Yes Yes No Yes Yes Yes No No Yes No
Yes Yes Yes Yes Yes Yes Yes Yes No Yes
Yes Yes Yes Yes Yes Yes Yes Yes No Yes
Reset-synchronized No PWM mode Complementary PWM mode Phase counting mode Buffer operation DMAC activation No No No
GRA0 comGRA1 comGRA2 comGRA3 comNo pare match or pare match or pare match or pare match or input capture input capture input capture input capture * Compare * Compare * Compare * Compare * Compare match/input match/input match/input match/input match/input capture A0 capture A1 capture A2 capture A3 capture A4 * Compare * Compare * Compare * Compare * Compare match/input match/input match/input match/input match/input capture B0 capture B1 capture B2 capture B3 capture B4 * Overflow * Overflow * Overflow * Overflow * Overflow
Interrupt sources (three)
RENESAS 215
10.1.2
Block Diagram
ITU Block Diagram (Complete): Figure 10.1 is the block diagram of the ITU.
TCLKA-TCLKD , /2, /4, /8 TOCXA4, TOCXB4 TIOCA0-TIOCA4 TIOCB0-TIOCB4
Clock selection
Control logic
IMIA0-IMIA4 IMIB0-IMIB4 OVI0-OVI4
Counter control and pulse I/O control unit
16-bit timer channel 4
16-bit timer channel 3
16-bit timer channel 2
16-bit timer channel 1
16-bit timer channel 0
TOCR TSTR TSNC TMDR TFCR Bus interface
Internal data bus
Module data bus
TOCR: Timer output control register (8 bits) TSTR: Timer start regsiter (8 bits) TSNC: Timer synchronization register (8 bits) TMDR: Timer mode register (8 bits) TFCR: Timer function control register (8 bits)
Figure 10.1 ITU Block Diagram
216 RENESAS
Block Diagram of Channels 0 and 1: ITU channels 0 and 1 have the same function. Figure 10.2 is a block diagram of channels 0 and 1.
TCLKA- TCLKD , /2, /4, /8
Clock selection
TIOCAn TIOCBn
Comparator
Control logic
IMIAn IMIBn OVIn
TCNTn
TIORn
TIERn
GRAn
GRBn
Module data bus TCNTn: Timer counter n (16 bits) GRAn, GRBn: General registers An, Bn (input capture/output compare dual use) (16 bits x 2) TCRn: Timer control register n (8 bits) TIORn: Timer I/O control register n (8 bits) TIERn: Timer interrupt enable register n (8 bits) TSRn: Timer status register n (8 bits) (n = 0 or 1)
Figure 10.2 Channels 0 and 1 Block Diagram (One Channel Shown)
TCRn
TSRn
RENESAS 217
Block Diagram of Channel 2: Figure 10.3 is a block diagram of channel 2. Channel 2 is 0 output/1 output only.
TCLKA- TCLKD , /2, /4, /8
Clock selection
TIOCA2 TIOCB2
Comparator
Control logic
IMIA2 IMIB2 OVI2
TCNT2
GRA2
GRB2
TIOR2
TIER2
Module data bus TCNT2: Timer counter 2 (16 bits) GRA2, GRB2: General registers A2, B2 (input capture/output compare dual use) (16 bits x 2) TCR2: Timer control register 2 (8 bits) TIOR2: Timer I/O control register 2 (8 bits) TIER2: Timer interrupt enable register 2 (8 bits) TSR2: Timer status register 2 (8 bits)
Figure 10.3 Channel 2 Block Diagram
218 RENESAS
TCR2
TSR2
Block Diagrams of Channels 3 and 4: Figure 10.4 is a block diagram of channel 3; figure 10.5 is a block diagram of channel 4.
TCLKA- TCLKD , /2, /4, /8
Clock selection
Comparator
Control logic
TIOCA3 TIOCB3 IMIA3 IMIB3 OVI3
TCNT3
TIOR3
TIER3
GRA3
BRA3
BRB3
GRB3
Module data bus TCNT3: Timer counter 3 (16 bits) GRA3, GRB3: General registers A3, B3 (input capture/output compare dual use) (16 bits x 2) BRA3, BRB3: Buffer registers A3, B3 (input capture/output compare dual use) (16 bits x 2) TCR3: Timer control register 3 (8 bits) TIOR3: Timer I/O control register 3 (8 bits) TIER3: Timer interrupt enable register 3 (8 bits) TSR3: Timer status register 3 (8 bits)
Figure 10.4 Channels 3 Block Diagram
TCR3
TSR3 RENESAS 219
TCLKA- TCLKD , /2, /4, /8
Clock selection
TOCXA4 TOCXB4 TIOCA4 TIOCB4 Control logic IMIA4 IMIB4 OVI4
Comparator
GCNT4
TIOR4
TIER4
GRA4
BRA4
BRB4
GRB4
Module data bus TCNT4: Timer counter 4 (16 bits) GRA4, GRB4: General registers A4, B4 (input capture/output compare dual use) (16 bits x 2) BRA4, BRB4: Buffer registers A4, B4 (input capture/output compare dual use) (16 bits x 2) TCR4: Timer control register 4 (8 bits) TIOR4: Timer I/O control register 4 (8 bits) TIER4: Timer interrupt enable register 4 (8 bits) TSR4: Timer status register 4 (8 bits)
Figure 10.5 Channel 4 Block Diagram
220 RENESAS
TCR4
TSR4
10.1.3
Input/Output Pins
Table 10.2 summarizes the ITU pins. External pin functions should be set with the pin function controller to match to the ITU setting. See section 15, Pin Function Controller, for details. ITU pins need to be set using the pin function controller (PFC) after the LSI is set to the ITU mode. Table 10.2 Pin Configuration
Channel Name Shared Clock input A Clock input B Clock input C Clock input D 0 Input capture/output compare A0 Input capture/output compare B0 1 Input capture/output compare A1 Input capture/output compare B1 2 Input capture/output compare A2 Input capture/output compare B2 3 Input capture/output compare A3 Input capture/output compare B3 4 Input capture/output compare A4 Input capture/output compare B4 Output compare XA4 Output compare XB4 Pin Name TCLKA TCLKB TCLKC TCLKD TIOCA0 TIOCB0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 I/O Function I I I I External clock A input pin (A-phase input pin in phase counting mode) External clock B input pin (B-phase input pin in phase counting mode) External clock C input pin External clock D input pin
I/O GRA0 output compare/GRA0 input capture/PWM output pin (in PWM mode) I/O GRB0 output compare/GRB0 input capture I/O GRA1 output compare/GRA1 input capture/PWM output pin (in PWM mode) I/O GRB1 output compare/GRB1 input capture I/O GRA2 output compare/GRA2 input capture/PWM output pin (in PWM mode) I/O GRB2 output compare/GRB2 input capture I/O GRA3 output compare/GRA3 input capture/PWM output pin (in PWM mode, complementary PWM mode, or reset-synchronized PWM mode) I/O GRB3 output compare/GRB3 input capture/PWM output pin (in complementary PWM mode or resetsynchronized PWM mode) I/O GRA4 output compare/GRA4 input capture/PWM output pin (in PWM mode, complementary PWM mode or reset-synchronized PWM mode) I/O GRB4 output compare/GRB4 input capture/PWM output pin (in complementary PWM mode or resetsynchronized PWM mode) I/O PWM output pin (in complementary PWM mode or reset-synchronized PWM mode) I/O PWM output pin (in complementary PWM mode or reset-synchronized PWM mode)
TIOCB3
TIOCA4
TIOCB4
TOCXA4 TOCXB4
RENESAS 221
10.1.4
Register Configuration
Table 10.3 summarizes the ITU register configuration. Table 10.3 Register Configuration
Channel Name Shared Timer start register Timer synchro register Timer mode register Abbreviation R/W TSTR TSNC TMDR R/W R/W R/W R/W R/W R/W R/W R/W R/(W)*2 R/W Initial Value Address* 1 Access Size 8 8 8 8 8 8 8 8 8 8, 16, 32 8, 16, 32
H'E0/H'60 H'5FFFF00 H'E0/H'60 H'5FFFF01 H'80/H'00 H'5FFFF02
Timer function control register TFCR Timer output control register 0 Timer control register 0 Timer I/O control register 0 Timer interrupt enable register 0 Timer status register 0 Timer counter 0 TOCR TCR0 TIOR0 TIER0 TSR0 TCNT0
H'C0/H'40 H'5FFFF03 H'FF/H'7F H'5FFFF31 H'80/H'00 H'88/H'08 H'5FFFF04 H'5FFFF05
H'F8/H'78 H'5FFFF06 H'F8/H'78 H'5FFFF07 H'00 H'5FFFF08 H'5FFFF09
General register A0
GRA0
R/W
H'FF
H'5FFFF0A 8, 16, 32 H'5FFFF0B 8, 16, 32
General register B0
GRB0
R/W
H'FF
H'5FFFF0C 8, 16 H'5FFFF0D 8, 16
1
Timer control register 1 Timer I/O control register 1 Timer interrupt enable register 1 Timer status register 1 Timer counter 1
TCR1 TIOR1 TIER1 TSR1 TCNT1
R/W R/W R/W R/(W)*2 R/W
H'80/H'00 H'88/H'08
H'5FFFF0E 8 H'5FFFF0F 8 8 8 8, 16 8, 16 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32
H'F8/H'78 H'5FFFF10 H'F8/H'78 H'5FFFF11 H'00 H'5FFFF12 H'5FFFF13
General register A1
GRA1
R/W
H'FF
H'5FFFF14 H'5FFFF15
General register B1
GRB1
R/W
H'FF
H'5FFFF16 H'5FFFF17
222 RENESAS
Table 10.3 Register Configuration (cont)
Channel Name 2 Timer control register 2 Timer I/O control register 2 Abbreviation R/W TCR2 TIOR2 R/W R/W R/W R/(W)*2 R/W Initial Value H'80/H'00 H'88/H'08 Address* 1 H'5FFFF18 H'5FFFF19 Access Size 8 8
Timer interrupt enable register TIER2 2 Timer status register 2 Timer counter 2 TSR2 TCNT2
H'F8/H'78 H'5FFFF1A 8 H'F8/H'78 H'5FFFF1B 8 H'00 H'5FFFF1C 8, 16, 32 H'5FFFF1D 8, 16, 32
General register A2
GRA2
R/W
H'FF
H'5FFFF1E 8, 16, 32 H'5FFFF1F 8, 16, 32 8, 16 8, 16 8 8 8 8 8, 16 8, 16 8, 16, 32 8, 16, 32
General register B2
GRB2
R/W
H'FF
H'5FFFF20 H'5FFFF21
3
Timer control register 3 Timer I/O control register 3
TCR3 TIOR3
R/W R/W R/W R/(W)*2 R/W
H'80/H'00 H'88/H'08
H'5FFFF22 H'5FFFF23
Timer interrupt enable register TIER3 3 Timer status register 3 Timer counter 3 TSR3 TCNT3
H'F8/H'78 H'5FFFF24 H'F8/H'78 H'5FFFF25 H'00 H'5FFFF26 H'5FFFF27
General register A3
GRA3
R/W
H'FF
H'5FFFF28 H'5FFFF29
General register B3
GRB3
R/W
H'FF
H'5FFFF2A 8, 16, 32 H'5FFFF2B 8, 16, 32
Buffer register A3
BRA3
R/W
H'FF
H'5FFFF2C 8, 16, 32 H'5FFFF2D 8, 16, 32
Buffer register B3
BRB3
R/W
H'FF
H'5FFFF2E 8, 16, 32 H'5FFFF2F 8, 16, 32 8 8 8 8
4
Timer control register 4 Timer I/O control register 4
TCR4 TIOR4
R/W R/W R/W R/(W)*2
H'80/H'00 H'88/H'08
H'5FFFF32 H'5FFFF33
Timer interrupt enable register TIER4 4 Timer status register 4 TSR4
H'F8/H'78 H'5FFFF34 H'F8/H'78 H'5FFFF35
RENESAS 223
Table 10.3 Register Configuration (cont)
Channel Name 4 (cont) Timer counter 4 Abbreviation R/W TCNT4H R/W Initial Value H'00 Address* 1 H'5FFFF36 H'5FFFF37 General register A4 GRA4H R/W H'FF H'5FFFF38 H'5FFFF39 General register B4 GRB4H R/W H'FF Access Size 8, 16 8, 16 8, 16, 32 8, 16, 32
H'5FFFF3A 8, 16, 32 H'5FFFF3B 8, 16, 32
Buffer register A4
BRA4H
R/W
H'FF
H'5FFFF3C 8, 16, 32 H'5FFFF3D 8, 16, 32
Buffer register B4
BRB4H
R/W
H'FF
H'5FFFF3E 8, 16, 32 H'5FFFF3F 8, 16, 32
Notes: 1. Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Description of Areas. 2. Write 0 to clear flags.
10.2
10.2.1
ITU Register Descriptions
Timer Start Register (TSTR)
The timer start register (TSTR) is an eight-bit read/write register that starts and stops the timer counters (TCNT) of channels 0-4. TSTR is initialized to H'E0 or H'60 upon reset or standby mode.
Bit: Bit name: Initial value: R/W: Note: Undefined 7 -- * -- 6 -- 1 -- 5 -- 1 -- 4 STR4 0 R/W 3 STR3 0 R/W 2 STR2 0 R/W 1 STR1 0 R/W 0 STR0 0 R/W
*
Bits 7-5 (reserved): Cannot be modified. Bit 7 is read as undefined. Bits 6 and 5 are always read as 1. The write value to bit 7 should be 0 or 1, and the write value to bits 6 and 5 should always be 1.
224 RENESAS
*
Bit 4 (count start 4 (STR4)): STR4 starts and stops TCNT4.
Description TCNT4 is halted (initial value) TCNT4 is counting
Bit 4: STR4 0 1
*
Bit 3 (count start 3 (STR3)): STR3 starts and stops TCNT3.
Description TCNT3 is halted (initial value) TCNT3 is counting
Bit 3: STR3 0 1
*
Bit 2 (count start 2 (STR2)): STR2 starts and stops TCNT2.
Description TCNT2 is halted (initial value) TCNT2 is counting
Bit 2: STR2 0 1
*
Bit 1 (count start 1 (STR1)): STR1 starts and stops TCNT1.
Description TCNT1 is halted (initial value) TCNT1 is counting
Bit 1: STR1 0 1
*
Bit 0 (count start 0 (STR0)): STR0 starts and stops TCNT0.
Description TCNT0 is halted (initial value) TCNT0 is counting
Bit 0: STR0 0 1
RENESAS 225
10.2.2
Timer Synchro Register (TSNC)
The timer synchro register (TSNC) is an eight-bit read/write register that selects timer synchronizing modes for channels 0-4. Channels for which 1 is set to the corresponding bit will be synchronized. TSNC is initialized to H'E0 or H'60 upon reset or standby mode.
Bit: Bit name: Initial value: R/W: Note: Undefined 7 -- * -- 6 -- 1 -- 5 -- 1 -- 4 3 2 SYNC2 0 R/W 1 0
SYNC4 SYNC3 0 R/W 0 R/W
SYNC1 SYNC0 0 R/W 0 R/W
*
Bits 7-5 (reserved): Bit 7 is read as undefined. Bits 6 and 5 are always read as 1. The write value to bit 7 should be 0 or 1, and the write value to bits 6 and 5 should always be 1. Bit 4 (timer synchro 4 (SYNC4)): SYNC4 selects the synchronizing mode for channel 4.
Description The timer counter for channel 4 (TCNT4) operates independently (Preset/clear of TCNT4 is independent of other channels) (initial value) Channel 4 operates synchronously. Synchronized preset/clear of TNCT4 enabled.
*
Bit 4: SYNC4 0 1
*
Bit 3 (timer Synchro 3 (SYNC3)): SYNC3 selects the synchronizing mode for channel 3.
Description The timer counter for channel 3 (TCNT3) operates independently (Preset/clear of TCNT3 is independent of other channels) (initial value) Channel 3 operates synchronously. Synchronized preset/clear of TNCT3 enabled.
Bit 3: SYNC3 0 1
*
Bit 2 (timer synchro 2 (SYNC2)): SYNC2 selects the synchronizing mode for channel 2.
Description The timer counter for channel 2 (TCNT2) operates independently (Preset/clear of TCNT2 is independent of other channels) (initial value) Channel 2 operates synchronously. Synchronized preset/clear of TNCT2 enabled.
Bit 2: SYNC2 0 1
226 RENESAS
*
Bit 1 (timer synchro 1 (SYNC1)): SYNC1 selects the synchronizing mode for channel 1.
Description The timer counter for channel 1 (TCNT1) operates independently (Preset/clear of TCNT1 is independent of other channels) (initial value) Channel 1 operates synchronously. Synchronized preset/clear of TNCT1 enabled.
Bit 1: SYNC1 0 1
*
Bit 0 (timer synchro 0 (SYNC0)): SYNC0 selects the synchronizing mode for channel 0.
Description The timer counter for channel 0 (TCNT0) operates independently (Preset/clear of TCNT0 is independent of other channels) (initial value) Channel 0 operates synchronously. Synchronized preset/clear of TNCT0 enabled.
Bit 0: SYNC0 0 1
10.2.3
Timer Mode Register (TMDR)
The timer mode register (TMDR) is an eight-bit read/write register that selects the PWM mode for channels 0-4, sets the phase counting mode for channel 2, and sets the conditions for the overflow flag (OVF). TMDR is initialized to H'80 or H'00 by a reset or the standby mode.
Bit: Bit name: Initial value: R/W: Note: Undefined 7 -- * -- 6 MDF 0 R/W 5 FDIR 0 R/W 4 PWM4 0 R/W 3 PWM3 0 R/W 2 PWM2 0 R/W 1 PWM1 0 R/W 0 PWM0 0 R/W
* *
Bit 7 (reserved): Bit 7 is read as undefined. The write value should be 0 or 1. Bit 6 (phase counting mode (MDF)): MDF selects the phase counting mode for channel 2.
Description Channel 2 operates normally (initial value) Channel 2 operates in phase counting mode
Bit 6: MDF 0 1
RENESAS 227
When the MDF is set to 1 to select the phase counting mode, the timer counter (TCNT2) becomes an up/down counter and the TCLKA and TCLKB pins become count clock input pins. TCNT2 counts on both the rising and falling edges of TCLKA and TCLKB, with the increment/decrement chosen as follows:
Count Direction TCLKA pin TCLKB pin Rising L Decrement High Rising Falling High Low Falling Rising High High Falling Increment Falling Low Low Rising
In the phase counting mode, selections for external clock edge made in the CKEG1 and CKEG0 bits of the timer control register 2 (TCR2) and the selection for counter clock made in the TPSC2 -TPSC0 bits are ignored. The phase counting mode described above takes priority. Settings for counter clear conditions in the CCLR1 and CCLR0 bits of TCR2 and settings for timer I/O control register 2 (TIOR2), timer interrupt enable register (TIER2) and timer status register 2 (TSR2) compare match/input capture functions and interrupts, however, are valid even in the phase counting mode. * Bit 5 (flag direction (FDIR)): FDIR selects the setting condition for the overflow flag (OVF) in timer status register 2 (TSR2). This bit is valid no matter which mode channel 2 is operating in.
Description OVF of TSR2 is set to 1 when TCNT2 overflows or underflows (initial value) OVF of TSR2 is set to 1 when TCNT2 overflows
Bit 5: FDIR 0 1
*
Bit 4 (PWM Mode 4 (PWM4)): PWM4 selects the PWM mode for channel 4. When the PWM4 bit is set to 1 and the PWM mode entered, the TIOCA4 pin becomes a PWM output pin. 1 is output on a compare match of general register A4 (GRA4); 0 is output on a compare match of general register B4 (GRB4). When the complementary PWM mode or resetsynchronized PWM mode are set by the CMD1 and CMD0 bits of the timer function control register (TFCR), the setting of this bit is ignored in favor of the settings of CMD1 and CMD0.
Description Channel 4 operates normally (initial value) Channel 4 operates in PWM mode
Bit 4: PWM4 0 1
228 RENESAS
*
Bit 3 (PWM Mode 3 (PWM3)): PWM3 selects the PWM mode for channel 3. When the PWM3 bit is set to 1 and the PWM mode entered, the TIOCA3 pin becomes a PWM output pin. 1 is output on a compare match of general register A3 (GRA3); 0 is output on a compare match of general register B3 (GRB3). When the complementary PWM mode or resetsynchronized PWM mode are set by the CMD1 and CMD0 bits of the timer function control register (TFCR), the setting of this bit is ignored in favor of the settings of CMD1 and CMD0.
Description Channel 3 operates normally (initial value) Channel 3 operates in PWM mode
Bit 3: PWM3 0 1
*
Bit 2 (PWM Mode 2 (PWM2)): PWM2 selects the PWM mode for channel 2. When the PWM2 bit is set to 1 and the PWM mode entered, the TIOCA2 pin becomes a PWM output pin. 1 is output on a compare match of general register A2 (GRA2); 0 is output on a compare match of general register B2 (GRB2).
Description Channel 2 operates normally (initial value) Channel 2 operates in PWM mode
Bit 2: PWM2 0 1
*
Bit 1 (PWM Mode 1 (PWM1)): PWM1 selects the PWM mode for channel 1. When the PWM1 bit is set to 1 and the PWM mode entered, the TIOCA1 pin becomes a PWM output pin. 1 is output on a compare match of general register A1 (GRA1); 0 is output on a compare match of general register B1 (GRB1).
Description Channel 1 operates normally (initial value) Channel 1 operates in PWM mode
Bit 1: PWM1 0 1
*
Bit 0 (PWM Mode 0 (PWM0)): PWM0 selects the PWM mode for channel 0. When the PWM0 bit is set to 1 and the PWM mode entered, the TIOCA0 pin becomes a PWM output pin. 1 is output on a compare match of general register A0 (GRA0); 0 is output on a compare match of general register B0 (GRB0).
Description Channel 0 operates normally (initial value) Channel 0 operates in PWM mode
Bit 0: PWM0 0 1
RENESAS 229
10.2.4
Timer Function Control Register (TFCR)
The timer function control register (TFCR) is an 8-bit read/write register that selects complementary PWM/reset-synchronized PWM for channels 3 and 4 and sets the buffer operation. TFCR is initialized on a reset or standby mode to H'C0 or H'40.
Bit: Bit name: Initial value: R/W: Note: Undefined 7 -- * -- 6 -- 1 -- 5 CMD1 0 R/W 4 CMD0 0 R/W 3 BFB4 0 R/W 2 BFA4 0 R/W 1 BFB3 0 R/W 0 BFA3 0 R/W
*
Bits 7 and 6 (reserved): Bit 7 is read as undefined. Bit 6 is always read as 1. The write value to bit 7 should be 0 or 1. The write value to bit 6 should always be 1. Bits 5 and 4 (combination mode 1 and 0 (CMD1 and CMD0)): CMD1 and CMD0 select the complementary PWM mode or reset-synchronized mode for channels 3 and 4. Set the complementary PWM/reset-synchronized PWM mode while the timer counter (TCNT) being used is off. When these bits are used to set the complementary PWM/reset-synchronized PWM mode, they take priority over the PWM4 and PWM3 bits of the TMDR. While the complementary PWM/reset-synchronized PWM mode settings and the SYNC4 and SYNC3 bit settings of the timer synchro register (TSNC) are valid simultaneously, when the complementary PWM mode is set, channels 3 and 4 should not be set to operate simultaneously (SYNC 4 and SYNC 3 bits of TSNC should not both be set to 1).
Bit 4: CMD0 0 1 Description Channels 3 and 4 operate normally (initial value) Channels 3 and 4 operate normally Channels 3 and 4 operate together in complementary PWM mode Channels 3 and 4 operate together in reset-synchronized PWM mode
*
Bit 5: CMD1 0
1
0 1
*
Bit 3 (buffer mode B4 (BFB4)): BFB4 selects the buffer mode for GRB4 and BRB4 in channel 4.
Description GRB4 operates normally in channel 4 (initial value) GRB4 and BRB4 operate in buffer mode in channel 4
Bit 3: BFB4 0 1
230 RENESAS
*
Bit 2 (buffer mode A4 (BFA4)): BFA4 selects the buffer mode for GRA4 and BRA4 in channel 4.
Description GRA4 operates normally in channel 4 (initial value) GRA4 and BRA4 operate in buffer mode in channel 4
Bit 2: BFA4 0 1
*
Bit 1 (buffer mode B3 (BFB3)): BFB3 selects the buffer mode for GRB3 and BRB3 in channel 3.
Description GRB3 operates normally in channel 3 (initial value) GRB3 and BRB3 operate in buffer mode in channel 3
Bit 1: BFB3 0 1
*
Bit 0 (buffer Mode A3 (BFA3)): BFA3 selects the buffer mode for GRA3 and BRA3 in channel 3.
Description GRA3 operates normally in channel 3 (initial value) GRA3 and BRA3 operate in buffer mode in channel 3
Bit 0: BFA3 0 1
10.2.5
Timer Output Control Register (TOCR)
The timer output control register (TOCR) is an eight-bit read/write register that inverts the output level of the complementary PWM mode/reset-synchronized PWM mode. Setting bits OLS3 and OLS4 is valid in only the complementary PWM mode and reset-synchronized PWM mode. In other output situations, these bits are ignored. The TOCR is initialized to H'FF or H'7F by a reset or in the standby mode.
Bit: Bit name: Initial value: R/W: Note: Undefined 7 -- * -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 OLS4 1 R/W 0 OLS3 1 R/W
*
Bits 7-2 (reserved): Bit 7 is read as undefined. Bits 6-2 are always read as 1. The write value to bit 7 should be 0 or 1. The write value to bits 6-2 should always be 1.
RENESAS 231
*
Bit 1 (output level select 4 (OLS4)): OLS4 selects the output level of the complementary PWM mode or reset-synchronized PWM mode.
Description TIOCA3, TIOCA4, and TIOCB4 are inverted and output TIOCA3, TIOCA4, and TIOCB4 are output directly (initial value)
Bit 1: OLS4 0 1
*
Bit 0 (output level select 3 (OLS3)): OLS3 selects the output level of the complementary PWM mode or reset-synchronized PWM mode.
Description TIOCB3, TOCXA4, and TOCXB4 are inverted and output TIOCB3, TOCXA4, and TOCXB4 are output directly (initial value)
Bit 0: OLS3 0 1
10.2.6
Timer Counters (TCNT)
The ITU has five 16-bit timer counters (TCNT), one for each channel (table 10.4). Each TCNT is a 16-bit read/write counter that counts by input from a clock source. The clock source is selected by timer prescalar bits 2-0 (TPSC2-TPSC0) in the timer control register (TCR). TCNT0 and TCNT 1 are strictly upcounters. Up/down counting occurs for TCNT2 when the phase counting mode is selected, or for TCNT3 and TCNT 4 when complementary PWM mode is selected. In other modes, they are upcounters. The TCNT can be cleared to H'0000 by compare match with the corresponding general register A or B (GRA, GRB) or input capture to GRA or GRB (counter clear function). When the TCNT overflows (changes from H'FFFF-H'0000), the overflow flag (OVF) in the timer status register (TSR) is set to 1. The OVF of the corresponding channel TSR is also set to 1 when the TCNT underflows (changes from H'0000-H'FFFF). The TCNT is connected to the CPU by a 16-bit bus, so it can be written or read by either word access or byte access. The TCNT is initialized to H'0000 by a reset or in standby mode.
232 RENESAS
Table 10.4 Timer Counters (TCNT)
Channel 0 1 2 3 4 Abbreviation TCNT0 TCNT1 TCNT2 TCNT3 TCNT4 Phase counting mode: Increment/decrement All others: Increment Complementary PWM mode: Increment/decrement All others: Increment Function Increment counter
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W:
15
14
13
12
11
10
9
8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
10.2.7
General Registers A and B (GRA and GRB)
Each of the five ITU channels has two 16-bit general registers (GR) for a total of ten registers (table 10.5). Each GR is a 16-bit read/write register that can function as either an output compare register or an input capture register. The function is selected by settings in the timer I/O control register (TIOR). When a general register (GRA/GRB) is used as an output compare register, its value is constantly compared with the timer counter (TCNT) value. When the two values match (compare match), the IMFA/IMFB bit is set to 1 in the timer status register (TSR). If compare match output is selected in the TIOR, a specified value is output at the output compare pin. When a general register is used as an input capture register, an external input capture signal is detected and the TCNT value is stored. The IMFA/IMFB bit of the corresponding TSR is set to 1 at the same time. The valid edge or edges of the input capture signal are selected in the TIOR. The TIOR setting is ignored when set for the PWM mode, complementary PWM mode or resetsynchronized PWM mode.
RENESAS 233
General registers are connected to the CPU by a 16-bit bus, so general registers can be written or read by either word access or byte access. General registers are initialized to the output compare register (no pin output) by a reset or in standby mode. The initial value is H'FFFF. Table 10.5 General Registers A and B (GRA and GRB)
Channel 0 1 2 3 4 Abbreviation GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 GRA4, GRB4 Output compare/input capture dual register. Can also be set for buffer operation in combination with the buffer registers (BRA, BRB) Function Output compare/input capture dual register
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W:
15
14
13
12
11
10
9
8
1 R/W 7
1 R/W 6
1 R/W 5
1 R/W 4
1 R/W 3
1 R/W 2
1 R/W 1
1 R/W 0
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
10.2.8
Buffer Registers A and B (BRA, BRB)
Each buffer register is a 16-bit read/write register that is used in the buffer mode. The ITU has four buffer registers, two each for channels 3 and 4 (table 10.6). Buffer operation can be set independently by the timer function control register (TFCR) bits BFB4, BFA4, BFB3, and BFB3 bits. The buffer registers are paired with the general registers and their function changes automatically to match the function of its corresponding general register. The buffer registers are connected to the CPU by a 16-bit bus, so they can be written or read by either word or byte access. Buffer registers are initialized to H'FFFF by a reset or in standby mode.
234 RENESAS
Table 10.6 Buffer Registers A and B (BRA, BRB)
Channel 3 4 Abbreviation BRA3, BRB3 BRA4, BRB4 Function When used for buffer operation: When the corresponding GRA and GRB are output compare registers, the buffer registers function as output compare buffer registers that can automatically transfer the BRA and BRB values to GRA and GRB upon a compare match. When the corresponding GRA and GRB are input capture registers, the buffer registers function as input capture buffer registers that can automatically transfer the values stored until an input capture in the GRA and GRB to the BRA and BRB.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W:
15
14
13
12
11
10
9
8
1 R/W 7
1 R/W 6
1 R/W 5
1 R/W 4
1 R/W 3
1 R/W 2
1 R/W 1
1 R/W 0
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
10.2.9
Timer Control Register (TCR)
The TCR is an 8-bit read/write register that selects the timer counter clock, the edges of the external clock source, and the counter clear source. Each ITU channel has one TCR. TCR is initialized H'80 or H'00 by a reset or the standby mode (table 10.7). Table 10.7 Timer Control Register (TCR)
Channel 0 1 2 3 4 Abbreviation TCR0 TCR1 TCR2 TCR3 TCR4 Function The TCR controls the TCNTs. The TCRs have the same functions on all channels. When channel 2 is set for phase counting mode, setting the CKEG1, CKEG2 and TPSC2-TPSC0 bits will have no effect.
RENESAS 235
Bit: Bit name: Initial value: R/W: Note: Undefined
7 -- * --
6 CCLR1 0 R/W
5 CCLR0 0 R/W
4
3
2 TPSC2 0 R/W
1 TPSC1 0 R/W
0 TPSC0 0 R/W
CKEG1 CKEG0 0 R/W 0 R/W
* *
Bit 7 (reserved): Bit 7 is read as undefined. The write value should be 0 or 1. Bits 6 and 5 (counter clear 1 and 0 (CCLR1 and CCLR0)): CCLR1 and CCLR0 select the counter clear source.
Bit 6: Bit 5: CCLR1 CCLR0 Description 0 0 1 1 0 1 TCNT is not cleared (initial value) TCNT is cleared by general register A (GRA) compare match or input capture* 1 TCNT is cleared by general register B (GRB) compare match or input capture* 1 Synchronizing clear: TCNT is cleared in synchronization with clear of other timer counters operating in sync.* 2
Notes: 1. When GR is functioning as an output compare register, TCNT is cleared upon a compare match. When functioning as an input capture register, TCNT is cleared upon input capture. 2. The timer synchro register (TSNC) set the synchronization.
*
Bits 4 and 3 (external clock edge 1/0 (CKEG1 and CKEG0)): CKEG1 and CKEG0 select external clock input edges. When channel 2 is set for phase counting mode, settings of the CKEG1 and CKEG0 of the TCR are ignored and the phase counting mode operation takes priority.
Bit 3: CKEG 0 0 1 Description Count rising edges (initial value) Count falling edges Count both rising and falling edges
Bit 4: CKEG 1 0
1
--
*
Bits 2-0 (timer prescalar 2-0 (TPS2-TPS0)): TPS2-TPS0 select the counter clock source. When TPSC2 = 0 and an internal clock source is selected, the timer counts only falling edges. When TPSC2 = 1 and an external clock is selected, the count edge is as set by CKEG1 and CKEG0. When the phase counting mode is selected for channel 2 (MDF bit in the timer mode register is 1), the settings of TPSC2-TPSC0 of TCR2 are ignored and the phase counting operation takes priority.
236 RENESAS
Bit 2: Bit 1: Bit 0: TPSC2 TPSC1 TPSC0 Counter Clock (and cycle when = 10 MHz) 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock (initial value) Internal clock /2 Internal clock /4 Internal clock /8 External clock A (TCLKA) External clock B (TCLKB) External clock C (TCLKC) External clock D (TCLKD)
10.2.10
Timer I/O Control Register (TIOR)
The timer I/O control register (TIOR) is an eight-bit read/write register that selects the output compare or input capture function for the general registers GRA and GRB. It also selects the function of the TIOCA and TIOCB pins. If output compare is selected, the TIOR also selects the output settings. If input capture is selected, the TIOR also select the input capture edges. TIOR is initialized to H'88 or H'08 on a reset or standby mode. Each ITU channel has one TIOR (table 10.8). Table 10.8 Timer I/O Control Register (TIOR)
Channel 0 1 2 3 4 Abbreviation TIOR0 TIOR1 TIOR2 TIOR3 TIOR4 Function The TIOR controls the GRs. Some functions vary during PWM. When channels 3 and 4 are set for complementary PWM mode/reset-synchronized PWM mode, TIOR3 and TIOR4 settings are not valid.
Bit: Bit name: Initial value: R/W: Note: Undefined
7 -- * --
6 IOB2 0 R/W
5 IOB1 0 R/W
4 IOB0 0 R/W
3 -- 1 --
2 IOA2 0 R/W
1 IOA1 0 R/W
0 IOA0 0 R/W
*
Bit 7 (reserved): Bit 7 is read as undefined. The write value should be 0 or 1.
RENESAS 237
*
Bits 6-4 (I/O control B2-B0 (IOB2-IOB0)): IOB2-IOB0 selects the GRB function.
Bit 5: IOB1 0 Bit 4: IOB0 0 1 1 0 1 GRB Function GRB is an Compare match with pin output disabled (initial value) output compare 0 output at GRB compare match* 1 register 1 output at GRB compare match* 1 Output toggles at GRB compare match (1 output for channel 2 only)* 1,* 2 GRB is an input capture register GRB captures rising edge of input GRB captures falling edge of input GRB captures both edges of input
Bit 6: IOB2 0
1
0
0 1
1
0 1
Notes: 1. After reset, the value output is 0 until the first compare match occurs. 2. Channel 2 has no compare-match driven toggle output function. If it is set for toggle, 1 is automatically selected as the output.
* *
Bit 3 (reserved): Bit 3 always reads as 1. The write value should always be 1. Bits 2-0 (I/O control A2-A0 (IOA2-IOA0)): IOA2-IOA0 select the GRB function.
Bit 1: IOA1 0 Bit 0: IOA0 0 1 1 0 1 GRA Function GRA is an Compare match with pin output disabled (initial value) output compare 0 output at GRA compare match* 1 register 1 output at GRA compare match* 1 Output toggles at GRA compare match (1 output for channel 2 only)* 1,* 2 GRA is an input capture register GRA captures rising edge of input GRA captures falling edge of input GRA captures both edges of input
Bit 2: IOA2 0
1
0
0 1
1
0 1
Notes: 1. After reset, the value output is 0 until the first compare match occurs. 2. Channel 2 has no compare-match driven toggle output function. If it is set for toggle, 1 is automatically selected as the output.
238 RENESAS
10.2.11
Timer Status Register (TSR)
The timer status register (TSR) is an eight-bit read/write register containing flags that indicate timer counter (TCNT) overflow/underflow and general register (GRA/GRB) compare match or input capture. These flags are interrupt sources. If the interrupt is enabled by the corresponding bit in the timer interrupt enable register (TIER), an interrupt is requested of the CPU. TSR is initialized by a reset or standby mode to H'F8 or H'78. Each ITU channel has one TSR (table 10.9). Table 10.9 Timer Status Register (TSR)
Channel 0 1 2 3 4 Abbreviation TSR0 TSR1 TSR2 TSR3 TSR4 Function The TSR indicates input capture, compare match and overflow status.
Bit: Bit name: Initial value: R/W:
7 -- *1 --
6 -- 1 --
5 -- 1 --
4 -- 1 --
3 -- 1 --
2 OVF 0 R/(W)*2
1 IMFB 0 R/(W)*2
0 IMFA 0 R/(W)*2
Notes: 1. Undefined 2. Write 0 to clear the flag.
*
Bits 7-3 (reserved): Bit 7 is read as undefined. Bits 6-3 are always read as 1. The write value to bit 7 should be 0 or 1. The write value to bits 6-3 should always be 1. Bit 2 (overflow flag (OVF)): OVF indicates a TCNT overflow/underflow has occurred.
Description Clearing condition: Read OVF when OVF = 1, then write 0 in OVF (initial value) Setting condition: TCNT overflowed from H'FFFF-H'0000 or underflowed from H'0000-H'FFFF.
*
Bit 2: OVF 0 1
Note: A TCNT underflow occurs when the TCNT up/down counter is functioning. It may occur in the following cases: (1) When channel 2 is set in the phase counting mode (MDF bit of TMDR is 1), or (2) When channel 3 and 4 are set to the complementary PWM mode (CMD1 bit of TFCR is 1 and CMD0 bit is 0).
RENESAS 239
*
Bit 1 (input capture/compare match B (IMFB)): IMFB indicates a GRB compare match or input capture.
Description Clearing condition: Read IMFB when IMFB = 1, then write 0 in IMFB (initial value) Setting condition: * GRB is functioning as an output compare register and TCNT = GRB * GRB is functioning as an input capture register and the value of TCNT is transferred to GRB by an input capture signal
Bit 1: IMFB 0 1
*
Bit 0 (input capture/compare match A (IMFA)): IMFA indicates a GRA compare match or input capture.
Description Read IMFA when IMFA = 1, then write 0 in IMFA (initial value). Clearing condition: DMAC is activated by an IMIA interrupt (only channels 0-3) Setting condition: * GRA is functions as an output compare register and TCNT = GRA * GRA is functioning as an input capture register and the value of TCNT is transferred to GRA by an input capture signal
Bit 0: IMFA 0
1
10.2.12
Timer Interrupt Enable Register (TIER)
The timer status interrupt enable register (TIER) is an eight-bit read/write register that controls enabling/disabling of overflow interrupt requests and general register compare match/input capture interrupt requests. TIER is initialized by a reset or standby mode to H'F8 or H'78. Each ITU channel has one TIER (table 10.10). Table 10.10 Timer Interrupt Enable Register (TIER)
Channel 0 1 2 3 4 Abbreviation TIER0 TIER1 TIER2 TIER3 TIER4 Function The TIER controls interrupt enable/disable.
240 RENESAS
Bit: Bit name: Initial value: R/W: Note: Undefined
7 -- * --
6 -- 1 --
5 -- 1 --
4 -- 1 --
3 -- 1 --
2 OVIE 0 R/W
1 IMIEB 0 R/W
0 IMIEA 0 R/W
*
Bits 7-3 (reserved): Bit 7 is read as undefined. Bits 6-3 are always read as 1. The write value to bit 7 should be 0 or 1. The write value to bits 6-3 should always be 1. Bit 2 (overflow interrupt enable (OVIE)): When the TSR overflow flag (OVF) is set to 1, OVIE enables or disables interrupt requests from the OVF.
Description Disables interrupt requests by the OVF (initial value) 1 Enables interrupt requests from the OVF
*
Bit 2: OVIE 0
*
Bit 1 (input capture/compare match interrupt enable B (IMIEB)): When the IMFB bit of the TSR is set to 1, IMIEB enables or disables the interrupt requests from the IMFB.
Description Disables interrupt requests by the IMFB (IMIB) (initial value) Enables interrupt requests from the IMFB (IMIB)
Bit 1: IMIEB 0 1
*
Bit 0 (input capture/compare match interrupt enable A (IMIEA)): When the IMFA bit of the TSR is set to 1, IMIEA enables or disables the interrupt requests from the IMFA.
Description Disables interrupt requests by the IMFA (IMIA) (initial value) Enables interrupt requests from the IMFA (IMIA)
Bit 0: IMIEA 0 1
10.3
10.3.1
CPU Interface
16-Bit Accessible Registers
The timer counters (TCNT), general registers A and B (GRA, GRB), and buffer registers A and B (BRA, BRB) are 16-bit registers. The SH CPU can access these registers a word at a time using a 16-bit data bus. Byte access is also possible. Read and write operations performed on the TCNT in word units are shown in figures 10.6 and 10.7. Byte-unit read and write operations on TCNTH and TCNTL are shown in figures 10.8-10.11.
RENESAS 241
Internal data bus H CPU L Bus interface H L Module data bus
TCNTH
TCNTL
Figure 10.6 Accessing TCNT (CPU-TCNT (word))
Internal data bus H CPU L Bus interface H L Module data bus
TCNTH
TCNTL
Figure 10.7 Accessing TCNT (TCNT-CPU (word))
Internal data bus H CPU L Bus interface H L Module data bus
TCNTH
TCNTL
Figure 10.8 Accessing TCNT (CPU-TCNT (upper byte))
242 RENESAS
Internal data bus H CPU L Bus interface H L Module data bus
TCNTH
TCNTL
Figure 10.9 Accessing TCNT (CPU-TCNT (lower byte))
Internal data bus H CPU L Bus interface H L Module data bus
TCNTH
TCNTL
Figure 10.10 Accessing TCNT (TCNT-CPU (upper byte))
Internal data bus H CPU L Bus interface H L Module data bus
TCNTH
TCNTL
Figure 10.11 Accessing TCNT (TCNT-CPU (lower byte)) 10.3.2 8-Bit Accessible Registers
All registers other than the TCNT, general registers, and buffer registers are 8-bit registers. These are connected to the CPU by an 8-bit data bus. Figures 10.12 and 10.13 illustrate reading and writing in byte units with the timer control register (TCR). These registers must be accessed by byte access.
RENESAS 243
Internal data bus
CPU
Bus interface
Module data bus
TCR
Figure 10.12 TCR Access (CPU-TCR)
Internal data bus
CPU
Bus interface
Module data bus
TCR
Figure 10.13 TCR Access (TCR-CPU )
10.4
10.4.1
Description of Operation
Overview
The operation modes are described below. Ordinary Operation: Each channel has a timer counter (TCNT) and general register (GR). The TCNT is an upcounter and can also operate as a free-running counter, periodic counter or external event counter. General registers A and B (GRA and GRB) can be used as output compare registers or input capture registers. Synchronized Operation: The TCNT of a channel set for synchronized operation does a synchronized preset. When any TCNT of a channel operating in the synchronized mode is rewritten, the TCNTs of other channels are simultaneously rewritten as well. The CCLR1 and CCLR0 bits of the timer control register of multiple channels set for synchronous operation can be set to clear the TCNTs simultaneously.
244 RENESAS
PWM Mode: In PWM mode, a PWM waveform is output from the TIOCA pin. Output becomes 1 upon compare match A and 0 upon compare match B. GRA and GRB can be set so that the PWM waveform output has a duty cycle between 0% and 100%. When set for PWM mode, the GRA and GRB automatically become output compare registers. Reset-synchronized PWM Mode: Three pairs of positive and negative PWM waveforms can be obtained using channels 3 and 4 (the three phases of the PWM waveform share a transition point on one side). When set for reset-synchronized PWM mode, GRA3, GRB3, GRA4, and GRB4 automatically become output compare registers. The TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 pins also automatically become PWM output pins and TCNT3 becomes an upcounter. TCNT4 functions independently (although GRA and GRB are isolated from TCNT4). Complementary PWM Mode: Three pairs of complementary positive and negative PWM waveforms whose positive and negative phases do not overlap can be obtained using channels 3 and 4. When set for complementary PWM mode, GRA3, GRB3, GRA4, and GRB4 automatically become output compare registers. The TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 pins also automatically become PWM output pins while TCNT3 and TCNT4 become upcounters. Phase Counting Mode: In phase counting mode, the phase differential between two clocks input from the TCLKA and TCLKB pins is detected and the TCNT2 operates as an up/downcounter. In phase counting mode, the TCLKA and TCLKB pins become clock inputs and TCNT2 functions as an up/downcounter. Buffer Mode: * * When GR is an output compare register: The BR value of each channel is transferred to the GR when a compare match occurs. When GR is an input capture register: The TCNT value is transferred to the GR when an input capture occurs and simultaneously the value previously stored in the GR is transferred to the BR. Complementary PWM mode: When the TCNT3 and TCNT4 change count directions, the BR value is transferred to the GR. Reset-synchronized PWM mode: The BR value is transferred to GR upon a GRA3 compare match. Basic Functions
* *
10.4.2
Counter Operation: When a start bit (STR0-STR4) in the timer start register (TSTR) is set to 1, the corresponding timer counter (TCNT) starts counting. There are two counting modes: a freerunning mode and a periodic mode.
RENESAS 245
*
Procedure for selecting counting mode (figure 10.14): 1. Set bits TPSC2-TPSC0 in the TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in the TCR to select the desired edges of the external clock signal. 2. To operate as a periodic counter, set CCLR1 and CCLR0 in the TCR to select whether to clear the TCNT at GRA compare match or GRB compare match. 3. Set the GRA or GRB selected in step 2 as an output compare register using the timer I/O control register (TIOR). 4. Write the desired cycle value in the GRA or GRB selected in step 1. 5. Set the STR bit in the TSTR to 1 to start counting.
Counting mode selection Select counter clock (1) No
Counting? Yes Periodic counter Select counter clear source Select output compare register Set period Start counting Periodic counter
Free-running counter
(2)
(3)
(4) (5) Start counting Free-running counter (5)
Figure 10.14 Procedure for Selecting the Counting Mode
246 RENESAS
*
Free-running count and periodic count A reset of the counters for channels 0-4 leaves them all in the free-running mode. When a corresponding bit in the TSTR is set to 1, the corresponding timer counter operates as a freerunning counter and begins to increment. When the count wraps around from H'FFFF-H'0000, the overflow flag (OVF) in the timer status register (TSR) is set to 1. If the OVIE bit in the timer's corresponding interrupt enable register (TIER) is set to 1, the CPU will be asked for an interrupt. After the TCNT overflows, counting continues from H'0000. Figure 10.15 shows an example of free-running counting. Periodic counter operation is obtained for a given channel's TCNT by selecting compare match as a TCNT clear source. (Set the GRA or GRB for period setting to output compare register and select counter clear upon compare match using the CCLR1 and CCLR0 bits of the timer control register (TCR).) After setting, the TCNT begins incrementing as a periodic counter when the corresponding bit of TSTR is set to 1. When the count matches GRA or GRB, the IMFA/IMFB bit in the TSR is set to 1 and the counter is automatically cleared to H'0000. If the IMIEA/IMIEB bit of the corresponding TIER is set to 1 at this point, the CPU will be asked for an interrupt. After the compare match, TCNT continues counting from H'0000. Figure 10.16 shows an example of periodic counting.
TCNT value H'FFFF H'0000 Time
STR0-STR4 OVF
Figure 10.15 Free-Running Counter Operation
RENESAS 247
TCNT value GR H'0000
Counter cleared by GR compare match
Time
STR0-STR4
IMF
Figure 10.16 Periodic Counter Operation * TCNT counter timing Internal clock source: Bits TPSC2-TPSC0 in the TCR select the system clock (CK) or one of three internal clock sources (/2, /4, /8) obtained by prescaling the system clock. Figure 10.17 shows the timing. External clock source: The external clock input pin (TCLKA-TCLKD) source is selected by bits TPSC2-TPSC0 in the TCR and its valid edges are selected with the CKEG1 and CKEG0 bits of the TCR. The rising edge, falling edge, or both edges can be selected. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be counted correctly. Figure 10.18 shows the timing when both edges are detected.
CK Internal clock TCNT input clock TCNT value N-1 N N+1
Figure 10.17 Count Timing for Internal Clock Sources
248 RENESAS
CK External clock input pin TCNT input clock TCNT N-1 N N+1
Figure 10.18 Count Timing for External Clock Sources Compare-Match Waveform Output Function: For ITU channels 0, 1, 3, and 4, the output from the corresponding TIOCA and TIOCB pins upon compare matches A and B can be in three modes: 0-level output, 1-level output, or toggle. Toggle output cannot be selected in channel 2. * Procedure for selecting the waveform output mode (figure 10.19): 1. Set the TIOR to select 0 output, 1 output, or toggle output for compare match output. The compare match output pin will output 0 until the first compare match occurs. 2. Set a value in the GRA or GRB to select the compare match timing. 3. Set the STR bit in the TSTR to 1 to start counting.
Output selection Select waveform output mode Select output timing Start counting
(1)
(2)
(3)
Waveform output
Figure 10.19 Procedure for Selecting the Compare Match Waveform Output Mode
RENESAS 249
*
Waveform output operation Figure 10.20 illustrates 0 output/1 output. In the example, TCNT is a free-running counter, 0 is output upon compare match A and 1 is output upon compare match B. When the pin level matches the set level, the pin level does not change. Figure 10.21 shows an example of toggle output. In the figure, the TCNT operates as a periodic counter cleared by GRB compare match with toggle output at both compare match A and compare match B.
TCNT value H'FFFF GRB GRA Time TIOCB Does not change Does not change 1 output
TIOCA Does not change Does not change 0 output
Figure 10.20 Example of 0 Output/1 Output
250 RENESAS
TCNT value GRB
Counter cleared at GRB compare match
GRA
Time TIOCB Toggle output Toggle output
TIOCA
Figure 10.21 Example of Toggle Output
RENESAS 251
*
Compare match output timing The compare match signal is generated in the last state in which the TCNT and the general register match (when the TCNT changes from the matching value to the next value). When a compare match signal is generated, the output value set in TIOR is output to the output compare pin (TIOCA, TIOCB). Accordingly, when the TCNT matches a general register, the compare match signal is not generated until the next counter clock pulse. Figure 10.22 shows the output timing of the compare match signal.
CK TCNT input clock TCNT N N-1
GR Compare match signal TIOCA TIOCB
N
Figure 10.22 Compare Match Signal Output Timing
252 RENESAS
Input Capture Mode: In the input capture mode, the counter value is captured into a general register when the input edge is detected at an input capture/output compare pin (TIOCA, TIOCB). Detection can take place on the rising edge, falling edge, or both edges. Pulse width and cycle can be measured by using the input capture function. * Procedure for selecting the input capture mode (figure 10.23) 1. Set the TIOR to select the input capture function of the GR and select the rising edge, falling edge, or both edges as the input edge of the input capture signal. Put the corresponding port into input-capture using the pin function controller before setting the TIOR. 2. Set the STR bit in the TSTR to 1 to start the TCNT counting.
Input selection Select input-capture input Start counting
Capture
Figure 10.23 Procedure for Selecting Input Capture Mode
RENESAS 253
*
Input capture operation Figure 10.24 illustrates input capture. The falling edge of TIOCB and both edges of TIOCA are selected as input capture edges. In the example, TCNT is set to clear at the input capture of GRB.
TCNT value H'0180 H'0160
Counter cleared by TIOCB input (falling edge)
H'0005 H'0000 TIOCB
Time
TIOCA
GRA
H'0005
H'0160
GRB
H'0180
Figure 10.24 Input Capture Operation
254 RENESAS
*
Input capture timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in the TIOR. Figure 10.25 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges.
CK Input capture input Input capture signal
TCNT
N
GRA/GRB
N
Figure 10.25 Input Capture Signal Timing
RENESAS 255
10.4.3
Synchronizing Mode
In the synchronizing mode, two or more timer counters can be rewritten simultaneously (synchronized preset). Multiple timer counters can also be cleared simultaneously using TCR settings (synchronized clear). The synchronizing mode can increase the general registers for a single time base. All five channels can be set for synchronous operation. Procedure for Selecting the Synchronizing Mode (figure 10.26): 1. Set 1 in the SYNC bit of the timer synchro register (TSNC) to use the channels in the synchronizing mode. 2. When a value is written in the TCNT in any of the synchronized channels, the same value is simultaneously written in the TCNT in the other channels. 3. Set the counter to clear with compare match/input capture using bits CCLR1 and CCLR0 in the TCR. 4. Set the counter clear source to synchronized clear using the CCLR1 and CCLR0 bits. 5. Set the STR bits in the TSTR to 1 to start counting in the TCNT.
Select synchronizing mode Set synchronizing mode Synchronized preset (1) Synchronized clear Channel that generated clear source? Yes Select counter clear source Start counting Synchronizing preset Counter clear Synchronized clear No
Set TCNT
(2)
(3)
Select counter clear source Start counting
(4)
(5)
(5)
Figure 10.26 Procedure for Selecting the Synchronizing Mode
256 RENESAS
Synchronized Operation: Figure 10.27 shows an example of synchronized operation. Channels 0, 1, and 2 are set to synchronized operation and PWM output. Channel 0 is set for a counter clear upon compare match with GRB0. Channels 1 and 2 are set for counter clears by synchronizing clears. Accordingly, their timers are sync preset, then sync cleared by a GRB0 compare match, and then a three-phase PWM waveform is output from the TIOCA0, TIOCA1 and TIOCA2 pins. See section 10.4.4, PWM Mode, for details on the PWM mode.
TCNT0-TCNT2 values
Synchronized clear on GRB0 compare match
GRB0 GRB1 GRA0 GRB2 GRA1 GRA2 Time TIOCA0
TIOCA1 TIOCA2
Figure 10.27 Synchronized Operation Example
RENESAS 257
10.4.4
PWM Mode
The PWM mode is controlled using both the GRA and GRB in pairs. The PWM waveform is output from the TIOCA output pin. The PWM waveform's 1 output timing is set in GRA and the 0 output timing is set in GRB. A PWM waveform with duty cycle between 0% and 100% can be output from the TIOCA pin by having either compare match GRA or GRB be the counter clear source for the timer counter. All five channels can be set to PWM mode. Table 10.11 lists the combinations of PWM output pins and registers. Note that when the GRA and GRB are set to the same value, the output will not change even if a compare match occurs. Table 10.11 Combinations of PWM Output Pins and Registers
Channel 0 1 2 3 4 Output Pin TIOCA0 TIOCA1 TIOCA2 TIOCA3 TIOCA4 1 Output GRA0 GRA1 GRA2 GRA3 GRA4 0 Output GRB0 GRB1 GRB2 GRB3 GRB4
Procedure for Selecting the PWM Mode (figure 10.28): 1. Set bits TPSC2-TPSC0 in the TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in the TCR to select the desired edges of the external clock signal. 2. Set CCLR1 and CCLR0 in the TCR to select the counter clear source. 3. Set the time at which the PWM waveform should go to 1 in the GRA. 4. Set the time at which the PWM waveform should go to 0 in the GRB. 5. Set the PWM bit in TMDR to select the PWM mode. When the PWM mode is selected, regardless of the contents of TIOR, the GRA and GRB become output compare registers specifying the times at which the PWM waveform goes high and low. TIOCA automatically becomes a PWM output pin. TIOCB becomes whatever is set in the TIOR's IOB1 and IOB0 bits. 6. Set the STR bit in the TSTR to let the TCNT start counting.
258 RENESAS
PWM mode
Select counter clock
(1)
Select counter clear source
(2)
Set GRA
(3)
Set GRB
(4)
Select PWM mode
(5)
Start counting
(6)
PWM mode
Figure 10.28 Procedure for Selecting the PWM Mode PWM Mode Operation: Figure 10.29 illustrates PWM mode operations. When the PWM mode is set, the TIOCA pin becomes the output pin. Output is 1 when the TCNT matches the GRA, and 0 when the TCNT matches the GRB. The TCNT can be cleared by compare match with either GRA or GRB. This can be used in both free-running and synchronized operation. Figure 10.30 shows examples of PWM waveforms output with 0% and 100% duty cycles. A 0% duty waveform can be obtained by setting the counter clear source to GRB and then setting GRA to a larger value than GRB. A 100% duty waveform can be obtained by setting the counter clear source to GRA and then setting GRB to a larger value than GRA.
RENESAS 259
TCNT value GRA
Counter cleared by GRA compare match
GRB
Time
TIOCA a. Counter cleared by GRA
TCNT value GRB
Counter cleared by GRB compare match
GRA
Time
TIOCA b. Counter cleared by GRB
Figure 10.29 PWM Mode Operation Example 1
260 RENESAS
TCNT value GRB
Counter cleared on compare match B
GRA
H'0000
Time
TIOCA
GRA write a. 0% duty
GRA write
TCNT value GRA
Counter cleared on compare match A
GRB
H'0000
Time
TIOCA
GRB write b. 100% duty
GRB write
Figure 10.30 PWM Mode Operation Example 2
RENESAS 261
10.4.5
Reset-Synchronized PWM Mode
In the reset-synchronized PWM mode, three pairs of complementary positive and negative PWM waveforms that share a common wave turning point can be obtained using channels 3 and 4. When set for reset-synchronized PWM mode, the TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 pins automatically become PWM output pins and TCNT3 becomes an upcounter. Table 10.12 shows the PWM output pins used and table 10.13 shows the settings of the registers used. Table 10.12 Output Pins for Reset-Synchronized PWM Mode
Channel 3 Output Pin TIOCA3 TIOCB3 4 TIOCA4 TOCXA4 TIOCB4 TOCXB4 Description PWM output 1 PWM output 1' (negative-phase waveform of PWM output 1) PWM output 2 PWM output 2' (negative-phase waveform of PWM output 2) PWM output 3 PWM output 3' (negative-phase waveform of PWM output 3)
Table 10.13 Register Settings for Reset-Synchronized PWM Mode
Register TCNT3 TCNT4 GRA3 GRB3 GRA4 GRB4 Description of Contents Initial setting of H'0000 Not used (functions independently) Set count cycle for TCNT3 Sets the turning point for PWM waveform output by the TIOCA3 and TIOCB3 pins Sets the turning point for PWM waveform output by the TIOCA4 and TOCXA4 pins Sets the turning point for PWM waveform output by the TIOCB4 and TOCXB4 pins
Procedure for Selecting the Reset-Synchronized PWM Mode (figure 10.31): 1. Clear the STR3 bits in the TSTR to halt TCNT3. The reset-synchronized PWM mode must be set up while TCNT3 is halted. 2. Set bits TPSC2-TPSC0 in the TCR to select the counter clock source for channel 3. If an external clock source is selected, select the external clock edges with bits CKEG1 and CKEG0 in the TCR. 3. Set bits CCLR1 and CCLR0 in the TCR3 to select GRA3 as a counter clear source. 4. Set bits CMD1 and CMD0 in TMDB to select the reset-synchronized PWM mode. TIOCA3- TIOCB4, TOCXA4, and TOCXB4 automatically become PWM output pins.
262 RENESAS
5. Reset the TCNT3 (to H'0000). The TCNT4 need not be set. 6. The GRA3 is the waveform period register. Set the waveform period value in the GRA3. Set the transition times of the PWM output waveforms in the GRB3, GRA4, and GRB4. Set times within the compare match range of the TCNT3.
X GRA3 (X: setting value)
7. Set the STR3 bits in the TSTR to 1 to let the TCNT3 start counting.
Reset synchronized PWM mode
Stop counting
(1)
Select counter clock
(2)
Select counter clear source
(3)
Select reset-synchronized PWM mode
(4)
Set TCNT
(5)
Set general registers
(6)
Start counting
(7)
Reset-synchronized PWM mode
Figure 10.31 Procedure for Selecting the Reset-Synchronized PWM Mode
RENESAS 263
Reset-Synchronized PWM Mode Operation: Figure 10.32 shows an example of operation in the reset-synchronized PWM mode. TCNT3 operates as an upcounter that is cleared to H'0000 at compare match with GRA3. TCNT4 runs independently and is isolated from GRA4 and GRB4. The PWM waveform outputs toggle at each compare match (GRB3, GRA3, and GRB4 with TCNT3) and when the counter is cleared. See section 10.4.8, Buffer Mode, for details on simultaneously setting reset-synchronized PWM mode and buffer operation.
TCNT value GRA3 GRB3 GRA4 GRB4
Counter cleared at GRA3 compare match
Time
TIOCA3 TIOCB3
TIOCA4 TOCXA4
TIOCB4 TOCXB4
Figure 10.32 Reset-Synchronized PWM Mode Operation Example 1 10.4.6 Complementary PWM Mode
In the complementary PWM mode, three pairs of complementary, non-overlapping, positive and negative PWM waveforms can be obtained using channels 3 and 4. In complementary PWM mode, the TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 pins automatically become PWM output pins and TCNT3 and TCNT4 become upcounters. Table 10.14 shows the PWM output pins used and table 10.15 shows the settings of the registers used.
264 RENESAS
Table 10.14 Output Pins for Complementary PWM Mode
Channel 3 Output Pin TIOCA3 TIOCB3 4 TIOCA4 TOCXA4 TIOCB4 TOCXB4 Description PWM output 1 PWM output 1' (non-overlapping negative-phase waveform of PWM output 1) PWM output 2 PWM output 2' (non-overlapping negative-phase waveform of PWM output 2) PWM output 3 PWM output 3' (non-overlapping negative-phase waveform of PWM output 3)
Table 10.15 Register Settings for Complementary PWM Mode
Register TCNT3 TCNT4 GRA3 GRB3 GRA4 GRB4 Description of Contents Initial setting of non-overlap cycle (the difference with TCNT4) Initial setting of H'0000 Set upper limit of TCNT3-1 Sets the turning point for PWM waveform output by the TIOCA3 and TIOCB3 pins. Sets the turning point for PWM waveform output by the TIOCA4 and TOCXA4 pins. Sets the turning point for PWM waveform output by the TIOCB4 and TOCXB4 pins.
Procedure for Selecting the Complementary PWM Mode (figure 10.33): 1. Clear STR3 and STR4 bits in the TSTR to halt the timer counters. The complementary PWM mode must be set up while TCNT3 and TCNT4 are halted. 2. Set bits TPSC2-TPSC0 in the TCR to select the same counter clock source for channels 3 and 4. If an external clock source is selected, select the external clock edges with bits CKEG1 and CKEG0 in the TCR. Do not select any counter clear source with bits CCLR1 and CCLR0 in the TCR. 3. Set bits CMD1 and CMD0 in TMDB to select the complementary PWM mode. TIOCA3- TIOCB4, TOCXA4, and TOCXB4 automatically become PWM pins. 4. Reset TCNT4 (to H'0000). Set the non-overlap offset in TCNT3. Do not set TCNT3 and TCNT4 to the same value.
RENESAS 265
5. GRA3 is the waveform period register. Set the upper limit of TCNT3-1*. Set the transition times of the PWM output waveforms in GRB3, GRA4, and GRB4. Set times within the compare match range of TCNT3 and TCNT4.
TX (X: initial setting of GRB3, GRA4, and GRB4; T: initial setting of TCNT3)
Note:
GRA3 = [cycle count/2] + [count of non-overlaps] - 2cyc=[upper limit of TCNT3] - 1
6. Set the STR3 and STR4 bits in the TSTR to 1 to let TCNT3 and TCNT4 start counting.
Complementary PWM mode
Stop counting
(1)
Select counter clock
(2)
Select complementary PWM mode
(3)
Set TCNT
(4)
Set general registers
(5)
Start counting
(6)
Complementary PWM mode Note To re-engage the complementary PWM mode after it has been aborted, start settings from step 1.
Figure 10.33 Procedure for Selecting the Complementary PWM Mode Complementary PWM Mode Operation: Figure 10.34 shows an example of operation in the complementary PWM mode. TCNT3 and TCNT4 operate as up/downcounters, counting down from compare match of TCNT3 and GRA3 and counting up when TCNT4 underflows. PWM waveforms are output by repeated compare matches with each of the general registers in the
266 RENESAS
sequence TCNT3, TCNT4, TCNT4, TCNT3 (in this mode, TCNT3 starts out larger than TCNT4). Figure 10.35 shows examples of PWM waveforms with 0% and 100% duty cycles (in one phase) in the complementary PWM mode. In this example, the pin output changes upon GRB3 compare match, so duty cycles of 0% and 100% can be obtained by setting GRB3 to a value larger than GRA3. Combining buffer operation with the above operation makes it easy to change the duty while operating. See section 10.4.8, Buffer Operation, for details.
TCNT3, TCNT4 value GRA3 GRB3 GRA4 GRB4
Down-counting starts at compare match between TCNT3 and GRA3 TCNT3
TCNT4 Time Up-counting starts at TCNT4 underflow TIOCA3 TIOCB3
TIOCA4 TOCXA4
TIOCB4 TOCXB4
Figure 10.34 Complementary PWM Mode Operation Example 1
RENESAS 267
TCNT3, TCNT4 value GRA3
GRB3
Time TIOCA3 TIOCB3 Duty 0% (a) With 0% duty
TCNT3, TCNT4 value GRA3
GRB3
Time TIOCA3 TIOCB3 Duty 100% (b) With 100% duty
Figure 10.35 Complementary PWM Mode Operation Example 2 At the point where the up-count/down-count changes in the complementary PWM mode, TCNT3 and TCNT4 will overshoot and undershoot, respectively. When this occurs, the setting conditions for the IMFA bit of channel 3 and the overflow flag (OVF) of channel 4 are different from usual. Transfer conditions for the buffer also differ. The timing is as shown in figures 10.36 and 10.37.
268 RENESAS
TCNT3
N-1
N
N+1
N
N-1
GRA3
N Flag not set
IMFA Set to 1 Buffer transfer signal (BR to GR) GR Buffer transfer performed Buffer transfer not performed
Figure 10.36 Overshoot Timing
Underflow TCNT4 H' 0001 H' 0000 H' FFFF H' 0000
Overflow
OVF Set to 1 Buffer transfer signal (BR to GR)
Flag not set
GR Buffer transfer performed Buffer transfer not performed
Figure 10.37 Undershoot Timing
RENESAS 269
The IMFA bit of channel 3 is set to 1 for increment pulses and the OVF bit of channel 4 is set to 1 for underflows only. The buffer register (BR) set for the buffer operation is transferred to the GR upon compare match A3 (when incrementing) or TCNT4 underflow. GR Setting in Complementary Mode: Be aware of the following when setting the general registers in complementary PWM mode and when making changes during operation. * * * Initial values: Setting H'0000 to T-1 (the initial setting T: TCNT3) is prohibited. After counting starts, this setting is allowed from the point when the first A3 compare match occurs. Methods of changing settings: Use the buffer operation. Writing directly to general registers may result in incorrect waveform output. When changing settings: See figure 10.38.
GRA3 GR
H' 0000 Prohibited BR GR
Figure 10.38 Example of Changing GR Settings with Buffer Operation (1)
270 RENESAS
Buffer Transfers when Changing from Increment to Decrement: When the contents of the GR are within GRA3 - T + 1 and GRA3, do not transfer a value outside this range. When the contents of GR are outside this range, do not a transfer a value within it. Figure 10.39 illustrates a point of caution regarding changing of GR settings with a buffer operation.
GRA3 + 1 GRA3 GRA3 - T + 1 GRA3 - T
Changes inhibited TCNT3 TCNT4
Figure 10.39 Caution for Changing GR Settings with Buffer Operation (1) Buffer Transfers when Changing from Decrement to Increment: When the contents of the GR are within H'0000 to T-1, do not transfer a value outside this range. When the contents of GR are outside this range, do not transfer a value within it. Figure 10.40 illustrates this point of caution regarding changing of GR settings with a buffer operation
TCNT3 TCNT4 T T-1 Changes inhibited H' 0000 H' FFFF
Figure 10.40 Caution for Changing GR Settings with Buffer Operation (2) When GR Settings are Outside the Count Range (H'0000-GRA3): Waveforms of duty cycle 0% and 100% can be output by setting GR outside the count area. Be sure to make the direction of the count (increment/decrement) when writing a setting from outside the count area into the buffer register (BR) the same as the count direction when writing the setting that returns to within the count area in the BR.
RENESAS 271
GRA3 GR
H' 0000 Duty 0% Duty 100%
Output pin Output pin
BR
GR Write on decrement Write on increment
Figure 10.41 Example of Changing GR Settings with Buffer Operation (2) The above settings are made by detecting the occurrence of a GRA3 compare match or underflow of TCNT4 and then writing to BR. They can also be accomplished by starting up the DMAC with a GRA3 compare match. 10.4.7 Phase Counting Mode
The phase counting mode detects the phase differential of two external clock inputs (TCLKA and TCLKB) and counts TCNT2 up or down. When set in the phase counting mode, the TCLKA and TCLKB pins automatically become external clock input pins, regardless of the settings of the TPSC2-TPSC0 bits of TCR2 or the CKEG1 and CKEG0 bits. TCNT2 also becomes an up/down counter. Since the TCR2 CCLR1/CCLR0 bits, TIOR2, TIER2, TSR2, GRA2 and GRB2 are all enabled, input capture and compare match functions and interrupt sources can be used. Phase counting is available only in channel 2. Procedure for Selecting the Phase Counting Mode: Figure 10.42 shows the procedure for selecting the phase counting mode. 1. Set the MDF bit of the timer mode register (TMDR) to 1 to select the phase counting mode. 2. Select the flag set conditions using the FDIR bit of the TMDR. 3. Set the STR2 bit of the timer start register (TSTR) to 1 to start the count.
272 RENESAS
Phase counting mode
Select phase counting mode
(1)
Select flag setting condition
(2)
Start counting
(3)
Phase counting mode
Figure 10.42 Procedure for Selecting the Phase Counting Mode Phase Counting Operation: Figure 10.43 shows an example of phase counting mode operation. Table 10.16 lists the upcounting and downcounting conditions for TCNT2. The ITU counts on both rise and fall edges of TCLKA and TCLKB. The phase differential and overlap of TCLKA and TCLKB must be 1.5 cycles or more and the pulse width must be 2.5 cycles or more.
TCNT2 value Increment Decrement
TCNT2 Time TCLKB TCLKA
Figure 10.43 Phase Counting Mode Operation Table 10.16 Up/Down Counting Conditions
Counting Direction TCLKB TCLKA Increment Rising Low High Rising Falling High Low Falling Decrement Rising High High Falling Falling Low Low Rising
RENESAS 273
Phase differential
Phase differential
Pulse width
Pulse width
TCLKA TCLKB
Overlap
Overlap Phase differential, overlap: 1.5 cycles minimum Pulse width: 2.5 cycles minimum
Figure 10.44 Phase Differentials, Overlap and Pulse Width in the Phase Counting Mode 10.4.8 Buffer Mode
In the buffer mode, the buffer operation functions differ depending on whether the general registers are set to output compare or input capture, the reset-synchronized PWM mode, or complementary PWM mode. The buffer mode is a function of channels 3 and 4 only. Buffer operations set this way function as follows. GR is an Output Compare Register: The value of the buffer registers of a channel is transferred to the GR when the channel experiences a compare match. This is illustrated in figure 10.45.
Compare match signal
BR
GR
Comparator
TCNT
Figure 10.45 Compare Match Buffer Operation GR is an Input Capture Register: TCNT values are transferred to GR when input capture occurs and the value previously stored in GR is transferred to BR. This operation is illustrated in figure 10.46.
274 RENESAS
Input capture signal
BR
GR
TCNT
Figure 10.46 Input Capture Buffer Operation Complementary PWM Mode: When the count direction of TCNT3 and TCNT4 change, the BR value is transferred to the GR. The following timing is employed for this transfer: * * Whenever TCNT3 and GRA3 compare-match Whenever TCNT4 underflows
Reset-Synchronized PWM Mode: The BR value is transferred to GR upon a GRA3 compare match. Procedure for Selecting the Buffer Mode (figure 10.47): 1. Set the TIOR to select the output compare or input capture function of the GR. 2. Set bits BFA3, BFB3 and BFB4 in the TFCR to select the buffer mode for the GR. 3. Set the STR bit in the TSTR to 1 to start the TCNT counting.
Buffer mode
Select general register function
(1)
Select buffer mode
(2)
Start counting
(3)
Buffer mode
Figure 10.47 Procedure for Selecting the Buffer Mode
RENESAS 275
Buffer Mode Operation: Figure 10.48 shows an example of an operation in the buffer mode with GRA set as an output compare register and GRA and buffer register A (BRA) set for buffer operation. The TCNT operates as a periodic counter that is cleared by GRB compare match. TIOCA and TIOCB are set to toggle at compare matches A and B. Since buffer mode is selected, when TIOCA toggles at a compare match A, the BRA value is simultaneously transferred to the GRA. This operation is repeated at every compare match A. The transfer timing is shown in figure 10.49.
TCNT value GRB H' 0250 H' 0200 H' 0100 H' 0000 BRA GRA TIOCB TIOCA H' 0200 H' 0250
Counter cleared by compare match B
Time H' 0100 H' 0200 H' 0100 H' 0200 H' 0200 Toggle output Toggle output Compare match A
Figure 10.48 Buffer Mode Operation Example 1 (Output Compare Register)
276 RENESAS
CK TCNT n n+1
Compare match signal Buffer transfer signal BR n N
N
GR
Figure 10.49 Compare Match Timing Example for Buffer Operation
RENESAS 277
Figure 10.50 shows an example of input capture operation in the buffer mode between GRA and BRA with GRA as an input capture register. The TCNT is cleared by input capture B. The falling edge is selected as the input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. When the TCNT value is stored in GRA by input capture A, the previous GRA value is transferred to the BRA. The timing is shown in figure 10.51.
TCNT value H' 0180 H' 0160
Counter cleared at input capture B
H' 0005 Time TIOCB TIOCA GRA BRA GRB H' 0005 H' 0160 H' 0005 H' 0160 H' 0180
Input capture A
Figure 10.50 Buffer Mode Operation Example 2 (Input Capture Register)
278 RENESAS
CK TIOC pin Input capture signal TCNT GR BR M m M n n n+1 N n M N n N+1
Figure 10.51 Input Capture Timing Example for Buffer Operation An example of buffer operation in the complementary PWM mode between GRB3 and BRB3 is as shown in figure 10.52. By making GRB3 larger than GRA3 using the buffer operation, a PWM waveform with a duty cycle of 0% is generated. The transfer from BRB-GRB occurs upon TCNT3 and GRA compare match and TCNT4 underflow.
TCNT3 and TCNT4 values TCNT3 H' 1FFF GRA3 GRB3
H' 0999 TCNT4
H' 0000 BRB3 H' 0999 H' 1FFF H' 1FFF H' 0999 H' 1FFF H' 0999
Time
GRB3
H' 0999
H' 0999
TIOCA3 TIOCB3
Figure 10.52 Buffer Operation 4 (Complementary PWM Mode)
RENESAS 279
10.4.9
ITU Output Timing
ITU outputs in channels 3 and 4 can be inverted with the TOCR. Output Inversion Timing with the TOCR: Output levels can be inverted by inverting the output level select bits (OLS4 and OLS3) of the TOCR in the complementary PWM mode and resetsynchronized PWM mode. Figure 10.53 illustrates the timing.
T1 CK
T2
T3
Address
TOCR address
TOCR
ITU output pin Inversion
Figure 10.53 Example of Inverting ITU Output Levels by Writing to TOCR
280 RENESAS
10.5
Interrupts
The ITU has two interrupt sources: input capture/compare match and overflow. 10.5.1 Timing of Setting Status Flags
Timing for Setting IMFA and IMFB in a Compare Match: The IMF bits of the TSR are set to 1 by a compare match signal generated when the TCNT matches a general register. The compare match signal is generated in the last state in which the values match (when the TCNT is updated from the matching count to the next count). Therefore, when the TCNT matches the GRA or GRB, the compare match signal is not generated until the next timer clock input. Figure 10.54 shows the timing of setting the IMF bits.
CK
TCNT input clock
TCNT
N
N+1
GR
N
Compare match signal
IMF
IMI
Figure 10.54 Timing of Setting Compare Match Flags (IMFA, IMFB)
RENESAS 281
Timing of Setting IMFA, IMFB for Input Capture: The IMFA and IMFB are set to 1 by an input capture signal. At this time, the TCNT contents are transferred to the GR. Figure 10.55 shows the timing.
CK
Input capture signal IMF
TCNT
N
GR
N
IMI
Figure 10.55 Timing of Setting IMFA and IMFB for Input Capture Timing of Setting Overflow Flag (OVF): The OVF is set to 1 when the TCNT overflows from H'FFFF-H'0000 or underflows from H'0000-H'FFFF. Figure 10.56 shows the timing.
282 RENESAS
CK
TCNT
H' FFFF
H' 0000
Overflow signal OVF
OVI
Figure 10.56 Timing of Setting OVF 10.5.2 Clear Timing of Status Flags
The status flags are cleared by a write cycle in which 1 is read on the CPU and then 0 is written to it. This timing is shown in figure 10.57.
TSR write cycle T1 T2 T3
CK
Address
TSR address
IMF, OVF
Figure 10.57 Timing of Status Flag Clearing
RENESAS 283
10.5.3
Interrupt Sources and Activating the DMAC
The ITU has compare match/input capture A interrupts, compare match/input capture B interrupts and overflow interrupts for each channel. Each of the fifteen of these three types of interrupts are allocated their own independently vectored addresses. When the interrupt's interrupt request flag is set to 1 and the interrupt enable bit is set to 1, the interrupt is requested. The channel priority order can be changed with the interrupt controller. For more information, see section 5, Interrupt Controller. The compare match/input capture A interrupts of channels 0-3 can start the DMAC to transfer data. Table 10.17 lists the interrupt sources. Table 10.17 ITU Interrupt Sources
Channel 0 Interrupt Source Description IMIA0 IMIB0 OVI0 1 IMIA1 IMIB1 OVI1 2 IMIA2 IMIB2 OVI2 3 IMIA3 IMIB3 OVI3 4 IMIA4 IMIB4 OVI4 Compare match or input capture A0 Compare match or input capture B0 Overflow 0 Compare match or input capture A1 Compare match or input capture B1 Overflow 1 Compare match or input capture A2 Compare match or input capture B2 Overflow 2 Compare match or input capture A3 Compare match or input capture B3 Overflow 3 Compare match or input capture A4 Compare match or input capture B4 Overflow 4 DMAC Activation Yes No No Yes No No Yes No No Yes No No No No No Low Priority Order* High
Note: Indicates the initial status following reset. The ranking of channels can be altered using the interrupt controller.
284 RENESAS
10.6
Notes and Precautions
This section describes contention and other matters requiring special attention during ITU operations. 10.6.1 Contention between TCNT Write and Clear
If a counter clear signal occurs in the T3 state of a TCNT write cycle, clearing the counter takes priority and the write is not performed. The timing is shown in figure 10.58.
TCNT write cycle by CPU T1 T2 T3
CK
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H' 0000
Figure 10.58 Contention between TCNT Write and Clear
RENESAS 285
10.6.2
Contention between TCNT Word Write and Increment
If an increment pulse occurs in the T3 state of a TCNT word write cycle, writing takes priority and the TCNT is not incremented. The timing is shown in figure 10.59.
TCNT word write cycle by CPU T1 T2 T3
CK
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N TCNT write data
M
Figure 10.59 Contention between TCNT Word Write and Increment
286 RENESAS
10.6.3
Contention between TCNT Byte Write and Increment
If an increment pulse occurs in the T2 state or T3 state of a TCNT byte write cycle, counter writing takes priority and the byte data on the side that was previously written is not incremented. The TCNT byte data that was not written is also not incremented and retains its previous value. The timing is shown in figure 10.60 (which shows an increment during state T2 of a byte write cycle to TCNTH).
TCNTH byte write cycle by CPU T1 CK T2 T3
Address
TCNTH address
Internal write signal
TCNT input clock
TCNTH
N TCNT write data
M
TCNTL
X
X+1
X
Figure 10.60 Contention between TCNT Byte Write and Increment
RENESAS 287
10.6.4
Contention between GR Write and Compare Match
If a compare match occurs in the T3 state of a general register (GR) write cycle, writing takes priority and the compare match signal is inhibited. The timing is shown in figure 10.61.
GR write cycle T1 T2 T3
CK
Address Internal write signal TCNT
GR address
N N
N+1 M GR write data
GR
Compare match signal
Inhibited
Figure 10.61 Contention between General Register Write and Compare Match
288 RENESAS
10.6.5
Contention between TCNT Write and Overflow/Underflow
If an overflow occurs in the T3 state of a TCNT write cycle, writing takes priority over counter incrementing. The OVF is set to 1. The same applies to underflows. This timing is shown in figure 10.62.
TCNT write cycle T1 T2 T3
CK Address Internal write signal TCNT input clock Overflow signal TCNT H'FFFF M TCNT write data OVF TCNT address
Figure 10.62 Contention between TCNT Write and Overflow
RENESAS 289
10.6.6
Contention between General Register Read and Input Capture
If an input capture signal is generated during the T3 state of a general register read cycle, the value before input capture is read. The timing is shown in figure 10.63.
GR read cycle T1 T2 T3
CK GR address
Address Internal read signal Input capture signal GR
X
M
Internal data bus
X
Figure 10.63 Contention between General Register Read and Input Capture
290 RENESAS
10.6.7
Contention Between Counter Clearing by Input Capture and Counter Increment
If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The TCNT value before the counter is cleared is transferred to the general register. The timing is shown in figure 10.64.
CK Input capture signal Counter clear signal TCNT input clock TCNT N H'0000
GR
N
Figure 10.64 Contention between Counter Clearing by Input Capture and Counter Increment
RENESAS 291
10.6.8
Contention between General Register Write and Input Capture
If an input capture signal is generated during the T3 state of a general register write cycle, the input capture transfer takes priority and the write to the GR is not performed. The timing is shown in figure 10.65.
GR write cycle T1 T2 T3
CK
Address Internal write signal Input capture signal TCNT
GR address
M
GR
M
Figure 10.65 Contention between General Register Write and Input Capture 10.6.9 Note on Waveform Cycle Setting
When a counter is cleared by compare match, the counter is cleared in the last state in which the TCNT value matches the GR value (when the TCNT is updated from the matching count to the next count). The actual counter frequency is therefore given by the following formula:
f = /(N + 1) (f: counter frequency. : operating frequency. N: value set in the GR.)
292 RENESAS
10.6.10
Contention Between BR Write and Input Capture
When a buffer register (BR) is being used as an input capture register and an input capture signal is generated in the T3 state of the write cycle, the buffer operation takes priority over the BR write. The timing is shown in figure 10.66.
BR write cycle T1 T2 T3
CK Address Internal write signal Input capture signal GR N X TCNT value BR M N BR address
Figure 10.66 Contention between BR Write and Input Capture
RENESAS 293
10.6.11
Note on Writing in the Synchronizing Mode
After the synchronizing mode is selected, if the TCNT is written by byte access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. Example: Figures 10.67 and 10.68 show byte write and word write when channels 2 and 3 are synchronized
TCNT2 TCNT3
W Y Upper byte
X Z Lower byte
Write A to upper byte of channel 2
TCNT2 TCNT3
A A Upper byte
X X Lower byte A A Lower byte
Write A to lower byte of channel 3 TCNT2 TCNT3
Y Y Upper byte
Figure 10.67
Byte Write to Channel 2 or Byte Write to Channel 3
TCNT2 TCNT3
W Y Upper byte
X Z Lower byte Word write of AB for channel 2 or 3
TCNT2 TCNT3
A A Upper byte
B B Lower byte
Figure 10.68 10.6.12
Word Write to Channel 2 or Word Write to Channel 3
Note on Setting Reset-synchronized PWM Mode/Complementary PWM Mode
When the CMD1 and CMD0 bits of TFCR are set, note the following. 1. Writes to CMD1 and CMD0 should be done while TCNT3 and TCNT4 are halted. 2. Changes of setting from the reset-synchronized PWM mode to the complementary PWM mode and vice versa are inhibited. Set the reset-synchronized PWM mode or complementary PWM mode after first setting normal operation (clear CMD1 bit to 0).
294 RENESAS
10.6.13
Clearing the Complementary PWM Mode
Figure 10.69 shows the procedure for clearing the complementary PWM mode. First, reset the combination mode bits CMD1 and CMD0 in the timer function control register (TFCR) from 10 to either 00 or 01. The mode will switch from complementary PWM mode to normal operating mode. Next, wait for at least 1 clock of the counter input clock being used for channels 3 and 4 and then clear the counter start bits STR3 and STR4 of the timer start register (TSTR). The channels 3 and 4 counters TCNT3 and TCNT4 will stop counting. Clearing the complementary PWM mode by any other procedure may result in changes other than those set for the output waveform when complementary PWM mode is set again.
Complementary PWM mode Clear complementary PWM mode 1. Clear the CMD1 bit of the TFCR to 0 to set channels 3 and 4 for normal operation 2. Wait at least 1 clock after setting channels 3 and 4 for normal operation and then clear the STR3 and STR4 bits of the TSTR to 0 to halt the TCNT3 and TCNT4 counters
Halt Count
Normal operation
Figure 10.69 Clearing the Complementary PWM Mode 10.6.14 ITU Operating Modes
Tables 10.18-10.22 show the ITU operating modes for channels 0-4. 10.6.15 Note on Counter Clearing by Input Capture
If TCNT is cleared (to H'0000) by input capture when its value is H'FFFF, overflow will not occur.
RENESAS 295
Table 10.18 ITU Operating Modes (Channel 0)
Register Setting TSNC Operating Mode Sync Synchronized preset PWM TMDR TFCR TOCR TIOR0 TCR0 Clear Clock Select Select
MDF FDIR PWM --
Reset Output Comp Sync Buf- Level PWM PWM fer Select IOA -- -- -- --
IOB
SYNC0 -- =1 -- --
-- --
PWM0 -- =1 PWM0 -- =0 --
-- --
-- --
-- --
--

Output compare A function Output compare B function Input capture A function Input capture B function Clear at compare match/ input capture A Clear at compare match/ input capture B Synchronized clear
IOA2 = 0, others free
--
--
--
--
--
IOB2 = 0, others free
--
--
PWM0 -- =0 PWM0 -- =0
--
--
--
IOA2 = 1, others free
--
--
--
--
--
IOB2 = 1, others free
Counter Clear Function -- -- -- -- -- -- CCLR1 =0 CCLR0 =1 CCLR1 =1 CCLR0 =0 CCLR1 =1 CCLR0 =1
--
--
--
--
--
--
SYNC0 -- =1
--
--
--
--
--
: Settable, --: Setting does not affect current mode Note: In PWM mode, the input capture function cannot be used. When compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
296 RENESAS
Table 10.19 ITU Operating Modes (Channel 1)
Register Setting TSNC Operating Mode Sync Synchronized preset PWM TMDR TFCR TOCR TIOR1 TCR1 Clear Clock Select Select
MDF FDIR PWM --
Reset Output Comp Sync Buf- Level PWM PWM fer Select IOA -- -- -- --
IOB
SYNC1 -- =1 -- --
-- --
PWM1 -- =1 PWM1 -- =0 --
-- --
-- --
-- --
--
*1

Output compare A function Output compare B function Input capture A function Input capture B function Clear at compare match/ input capture A Clear at compare match/ input capture B Synchronized clear
IOA2 = 0, others free
--
--
--
--
--
IOB2 = 0, others free
--
--
PWM1 -- =0 PWM1 -- =0
--
--
--
IOA2 = 1, others free
--
--
--
--
--
IOB2 = 1, others free
Counter Clear Function -- -- -- -- -- -- CCLR1 =0 CCLR0 =1 CCLR1 =1 CCLR0 =0 CCLR1 =1 CCLR0 =1
--
--
--
--
--
--
SYNC1 -- =1
--
--
--
--
--
: Settable, --: Setting does not affect current mode Note: In PWM mode, the input capture function cannot be used. When compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
RENESAS 297
Table 10.20 ITU Operating Modes (Channel 2)
Register Setting TSNC Operating Mode Sync Synchronized preset PWM TMDR TFCR TOCR TIOR2 TCR2 Clear Clock Select Select
MDF FDIR PWM --
Reset Output Comp Sync Buf- Level PWM PWM fer Select IOA -- -- -- --
IOB
SYNC2 -- =1 -- --
-- --
PWM2 -- =1 PWM2 -- =0 --
-- --
-- --
-- --
--

Output compare A function Output compare B function Input capture A function Input capture B function Clear at compare match/ input capture A Clear at compare match/ input capture B Synchronized clear Phase counting
IOA2 = 0, others free
--
--
--
--
--
IOB2 = 0, others free
--
--
PWM2 -- =0 PWM2 -- =0
--
--
--
IOA2 = 1, others free
--
--
--
--
--
IOB2 = 1, others free
Counter Clear Function -- -- -- -- -- -- CCLR1 =0 CCLR0 =1 CCLR1 =1 CCLR0 =0 CCLR1 =1 CCLR0 =1 --
--
--
--
--
--
--
SYNC2 -- =1
--
--
--
--
--
MDF =1
--
--
--
--
: Settable, --: Setting does not affect current mode
298 RENESAS
Note: In PWM mode, the input capture function cannot be used. When compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
Table 10.21 ITU Operating Modes (Channel 3)
Register Setting TSNC Operating Mode Sync Synchronized preset PWM mode TMDR TFCR TOCR TIOR3 TCR3 Clear Clock Select Select
MDF FDIR PWM --
Reset Output Comp Sync Buf- Level PWM PWM fer Select IOA *2 --
IOB
SYNC3 -- =1 -- --
-- --
PWM3 CMD1 CMD1 =1 =0 =0 PWM3 CMD1 CMD1 =0 =0 =0 CMD1 CMD1 =0 =0
-- --
--
*1

Output compare A function Output compare B function Input capture A function Input capture B function Clear at compare match/ input capture A Clear at compare match/ input capture B Synchronized clear
IOA2 = 0, others free
--
--
--
IOB2 = 0, others free
--
--
PWM3 CMD1 CMD1 =0 =0 =0 PWM3 CMD1 CMD1 =0 =0 =0
--
IOA2 = 1, others free
--
--
--
IOB2 = 1, others free
Counter Clear Function -- -- CMD1 *3 = 1, CMD0 =0 inhibited -- CCLR1 =0 CCLR0 =1
--
--
CMD1 CMD1 =0 =0
--
CCLR1 =1 CCLR0 =0 CCLR1 =1 CCLR0 =1
SYNC3 -- =1
--
CMD1 = 1, CMD0 =0 inhibited
--
RENESAS 299
Table 10.21 ITU Operating Modes (Channel 3) (cont)
Counter Clear Function Register Setting TSNC Operating Mode Sync Complementary PWM mode *2 TMDR TFCR TOCR Output Level Select IOA -- TIOR3 TCR3 Clear Clock Select Select CCLR1 *4 =0 CCLR0 =0 CCLR1 =0 CCLR0 =1
Reset Comp Sync BufMDF FDIR PWM PWM PWM fer -- -- -- CMD1 CMD1 =1 =1 CMD0 CMD0 =0 =0 CMD1 CMD1 =1 =1 CMD0 CMD0 =1 =1
IOB --
Reset synchronized PWM mode Buffer (BRA)
--
--
--
--
--
--
--
BFA3 -- = 1, others free BFB3 -- = 1, others free
Buffer (BRB)
--
--

: Settable, --: Setting does not affect current mode Notes: 1. In PWM mode, the input capture function cannot be used. When compare match A and compare match B occur simultaneously, the compare match signal is inhibited. 2. When set for complementary PWM mode, do not simultaneously set channel 3 and channel 4 to function synchronously. 3. Counter clearing by input capture A cannot be used when the reset-synchronized PWM mode is set. 4. Clock selection when the complementary PWM mode is set should be the same for channels 3 and 4.
300 RENESAS
Table 10.22 ITU Operating Modes (Channel 4)
Register Setting TSNC Operating Mode Sync Synchronized preset PWM TMDR TFCR TOCR TIOR4 TCR4 Clear Clock Select Select
MDF FDIR PWM --
Reset Output Comp Sync Buf- Level PWM PWM fer Select IOA *2 --
IOB
SYNC4 -- =1 -- --
-- --
PWM4 CMD1 CMD1 =1 =0 =0 PWM4 CMD1 CMD1 =0 =0 =0 CMD1 CMD1 =0 =0
-- --
--
*1

Output compare A function Output compare B function Input capture A function Input capture B function Clear at compare match/ input capture A Clear at compare match/ input capture B
IOA2 = 0, others free
--
--
--
IOB2 = 0, others free
--
--
PWM4 CMD1 CMD1 =0 =0 =0 PWM4 CMD1 CMD1 =0 =0 =0
--
IOA2 = 1, others free
--
--
--
IOB2 = 1, others free
Counter Clear Function -- -- CMD1 *3 = 1, CMD0 =0 inhibit ed CMD1 *3 = 1, CMD0 =0 inhibit ed -- CCLR1 =0 CCLR0 =1
--
--
--
CCLR1 =1 CCLR0 =0
RENESAS 301
Table 10.22 ITU Operating Modes (Channel 4) (cont)
Counter Clear Function Register Setting TSNC Operating Mode Sync Synchronized clear TMDR TFCR TOCR Output Level Select IOA -- TIOR4 TCR4 Clear Clock Select Select CCLR1 =1 CCLR0 =1
Reset Comp Sync BufMDF FDIR PWM PWM PWM fer -- CMD1 *3 = 1, CMD1 =0 inhibit ed
IOB
SYNC4 -- =1
Complementary PWM
*2
--
--
--
CMD1 CMD1 =1 =1 CMD0 CMD0 =0 =0 CMD1 CMD1 =1 =1 CMD0 CMD0 =1 =1
--
--
CCLR1 *4 =0 CCLR0 =0 *5 *5
Reset synchronized PWM Buffer (BRA)
--
--
--
--
--
--
--
BFA4 -- = 1, others free BFB4 -- = 1, others free

Buffer (BRB)
--
--

: Settable, --: Setting does not affect current mode Notes: 1. In PWM mode, the input capture function cannot be used. When compare match A and compare match B occur simultaneously, the compare match signal is inhibited. 2. When set for complementary PWM mode, do not simultaneously set channel 3 and channel 4 to function synchronously. 3. Counter clearing works with the reset-synchronized PWM mode, but TCNT4 runs independently. The output waveform is not affected. 4. Clock selection when the complementary PWM mode is set should be the same for channels 3 and 4. 5. In the reset-synchronized PWM mode, TCNT4 runs independently. The output waveform is not affected.
302 RENESAS
Section 11 Programmable Timing Pattern Controller (TPC)
11.1 Overview
The SuperH microcomputer has a built-in programmable timing pattern controller (TPC). The TPC can provide pulse outputs by using the 16-bit integrated-timer pulse unit (ITU) as a time base. The TPC pulse outputs are divided into 4-bit groups 3-0. These can operate simultaneously, or independently. 11.1.1 Features
Features of the programmable timing pattern controller are listed below. * * * * * * 16-bit output data: Maximum 16-bit data can be output. TPC output can be enabled on a bitby-bit basis. Four output groups: Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs. Selectable output trigger signals: Output trigger signals can be selected by group from the 4-channel compare-match signals of the 16-bit integrated-timer pulse unit (ITU). Non-overlap mode: A non-overlap interval can be set to come between multiple pulse outputs. Can connect to DMA controller: The compare-match signals selected as output trigger signals can activate the DMA controller for sequential output of data without CPU intervention.
RENESAS 303
11.1.2
Block Diagram
Figure 11.1 is the block diagram of the TPC.
ITU compare match signal
PBCR1 Control logic NDERA TPMR
PBCR2 NDERB TPCR
TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8 TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
Pulse output pin group 3 NDRB Pulse output pin group 2 PBDR Pulse output pin group 1 NDRA Pulse output pin group 0 TPC
Internal data bus
TPMR: TPC output mode register TPCR: TPC output control register NDERB: Next data enable register B NDERA: Next data enable register A
PBCR1: Port B control register 1 PBCR2: Port B control register 2 NDRB: Next data register B NDRA: Next data register A PBDR: Port B data register
Figure 11.1 TPC Block Diagram
304 RENESAS
11.1.3
Input/Output Pins
Table 11.1 summarizes the TPC input/output pins. Table 11.1 TPC Pins
Name TPC output 0 TPC output 1 TPC output 2 TPC output 3 TPC output 4 TPC output 5 TPC output 6 TPC output 7 TPC output 8 TPC output 9 TPC output 10 TPC output 11 TPC output 12 TPC output 13 TPC output 14 TPC output 15 Symbol TP0 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 Input/Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Group 3 pulse output Group 2 pulse output Group 1 pulse output Function Group 0 pulse output
RENESAS 305
11.1.4
Registers
Table 11.2 summarizes the TPC registers. Table 11.2 TPC Registers
Name Port B control register 1 Port B control register 2 Port B data register TPC output mode register TPC output control register Next data enable register B Next data enable register A Next data register A Next data register B Abbreviation PBCR1 PBCR2 PBDR TPMR TPCR NDERB NDERA NDRA NDRB R/W R/W R/W R/(W)*2 R/W R/W R/W R/W R/W R/W Initial Value H'0000 H'0000 H'0000 H'F0 H'FF H'00 H'00 H'00 H'00 Address* 1 H'5FFFFCC H'5FFFFCE H'5FFFFC2 H'5FFFFF0 H'5FFFFF1 H'5FFFFF2 H'5FFFFF3 H'5FFFFF5/ H'5FFFFF7*3 H'5FFFFF4/ H'5FFFFF6*3 Access Size 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16
Notes: 1. Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Description of Areas. 2. Bits used for TPC output cannot be written to. 3. These addresses change depending on TPCR settings. When TPC output groups 0 and 1 have the same output trigger, the NDRA address is H'5FFFFF5; when their output triggers are different, the NDRA address for group 0 is H'5FFFFF7 and the address for group 1 is H'5FFFFF5. Likewise, when TPC output groups 2 and 3 have the same output trigger, the NDRB address is H'5FFFFF4; when their output triggers are different, the NDRB address for group 0 is H'5FFFFF6 and the address for group 1 is H'5FFFFF4.
11.2
11.2.1
Register Descriptions
Port B Control Registers 1 and 2 (PBCR1, PCBR2)
The port B control register 1 and 2 (PBCR1 and PBCR2) are 16-bit read/write registers that set the functions of port B pins. Port B consists of the dual use pins TP15-TP0. Bits corresponding to the pins to be used for TPC output must be set to 1. For details, see the port B description in the section 15, Pin Function Controller.
306 RENESAS
PCBR1:
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 PB15 MD1 0 R/W 7 PB11 MD1 0 R/W 14 PB15 MD0 0 R/W 6 PB11 MD0 0 R/W 13 PB14 MD1 0 R/W 5 PB10 MD1 0 R/W 12 PB14 MD0 0 R/W 4 PB10 MD0 0 R/W 11 PB13 MD1 0 R/W 3 10 PB13 MD0 0 R/W 2 9 PB12 MD1 0 R/W 1 8 PB12 MD0 0 R/W 0
PB9MD1 PB9MD0 PB8MD1 PB8MD0 0 R/W 0 R/W 0 R/W 0 R/W
PCBR2:
Bit: 15 14 13 12 11 10 9 8
Bit name: PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0
Bit name: PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD1 PB1MD0 PB0MD1 PB0MD0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
11.2.2
Port B Data Register (PBDR)
The port B data register is a 16-bit read/write register that, when used for TPC output stores, output data for groups 0-3. For details, see the port B description in section 16, I/O Ports.
Bit: 15 14 13 12 11 10 9 8
Bit name: PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR PB8DR Initial value: R/W: 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)*
Note: Bits set to TPC output by NDERA or NDERB are read-only.
RENESAS 307
Bit: Bit name: Initial value: R/W:
7 PB7DR 0 R/(W)*
6
5
4
3
2 PB2DR 0 R/(W)*
1
0
PB6DR PB5DR 0 R/(W)* 0 R/(W)*
PB4DR PB3DR 0 R/(W)* 0 R/(W)*
PB1DR PB0DR 0 R/(W)* 0 R/(W)*
Note: Bits set to TPC output by NDERA or NDERB are read-only.
11.2.3
Next Data Register A (NDRA)
NDRA is an eight-bit read/write register that stores the next output data for TPC output groups 1 and 0 (TP7-TP0). When used for TPC output, the contents of the NDRA are transferred to the corresponding PBDR bits when the ITU compare match specified in the TPC output control register TPCR occurs. The address of the NDRA differs depending on whether TPCR settings select the same trigger or different triggers for TPC output groups 1 and 0. When reset, NDRA is initialized to H'00. It is not initialized by standby mode. Same Trigger for TPC Output Groups 1 and 0: If TPC output groups 1 and 0 are triggered by the same compare match, the address of the NDRA is H'FFFFF5. The 4 upper bits becomes group 1 and the 4 lower bits become group 0. Address H'5FFFFF7 in such cases consists entirely of reserved bits. These bits cannot be modified and always read as 1. Address H'5FFFFF5: * Bits 7-4 (next data 7-4 (NDR7-NDR4)): NDR7-NDR4 store the next output data for TPC output group 1. Bits 3-0 (next data 3-0 (NDR3-NDR0)): NDR3-NDR0 store the next output data for TPC output group 0.
Bit: Bit name: Initial value: R/W: 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W
*
308 RENESAS
Address H'5FFFFF7: * Bits 7-0 (reserved): These bits always read as 1. The write value should always be 1.
Bit: Bit name: Initial value: R/W: 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
Different Triggers for TPC Output Groups 1 and 0: If TPC output groups 1 and 0 are triggered by different compare matches, the address of the upper 4 bits of NDRA (group 1) is H'5FFFFF5 and the address of the lower 4 bits of NDRA (group 0) is H'5FFFFF7. Bits 3-0 of address H'5FFFFF5 and bits 7-4 of address H'5FFFFF7 are reserved bits. The write value should always be 1. These bits always read as 1. Address H'5FFFFF5: * Bits 7-4 (next data 7-4 (NDR7-NDR4)): NDR7-NDR4 store the next output data for TPC output group 1. Bits 3-0 (reserved): These bits always read as 1. The write value should always be 1.
Bit: Bit name: Initial value: R/W: 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
*
Address H'5FFFFF7: * * Bits 7-4 (reserved): These bits always read as 1. The write value should always be 1. Bits 3-0 (next data 3-0 (NDR3-NDR0)): NDR3-NDR0 store the next output data for TPC output group 0.
Bit: Bit name: Initial value: R/W: 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W
RENESAS 309
11.2.4
Next Data Register B (NDRB)
NDRB is an eight-bit read/write register that stores the next output data for TPC output groups 3 and 2 (TP15-TP8). When used for TPC output, the contents of the NDRB are transferred to the corresponding PBDR bits when the ITU compare match specified in the TPC output control register TPCR occurs. The address of the NDRB differs depending on whether TPCR settings select the same trigger or different triggers for TPC output groups 3 and 2. When reset, NDRB is initialized to H'00. It is not initialized by standby mode. Same Trigger for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered by the same compare match, the address of the NDRB is H'FFFFF4. The 4 upper bits becomes group 3 and the 4 lower bits become group 2. Address H'5FFFFF6 becomes completely reserved bits. These bits always read as 1, and the write value should always be 1. Address H'5FFFFF4: * Bits 7-4 (next data 15-12 (NDR15-NDR12)): NDR15-NDR12 store next output data for TPC output group 3. Bits 3-0 (next data 11-8 (NDR11-NDR8)): NDR11-NDR8 store next output data for TPC output group 2.
Bit: Bit name: Initial value: R/W: 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W
*
Address H'5FFFFF6: * Bits 7-0 (reserved): These bits always read as 1. The write value should always be 1.
Bit: Bit name: Initial value: R/W: 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
310 RENESAS
Different Triggers for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered by different compare matches, the address of the upper 4 bits of NDRB (group 3) is H'5FFFFF4 and the address of the lower 4 bits of NDRB (group 2) is H'5FFFFF6. Bits 3-0 of address H'5FFFFF4 and bits 7-4 of address H'5FFFFF6 are reserved bits. These bits always read as 1. The write value should always be 1. Address H'5FFFFF4: * Bits 7-4 (next data 15-12 (NDR15-NDR12)): NDR15-NDR12 store next output data for TPC output group 3. Bits 3-0 (reserved): These bits always read as 1. The write value should always be 1.
Bit: Bit name: Initial value: R/W: 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
*
Address H'5FFFFF6: * * Bits 7-4 (reserved): These bits always read as 1. The write value should always be 1. Bits 3-0 (next data 11-8 (NDR11-NDR8)): NDR11-NDR8 store next output data for TPC output group 2.
Bit: Bit name: Initial value: R/W: 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W
11.2.5
Next Data Enable Register A (NDERA)
NDERA is an eight-bit read/write register that enables TPC output groups 1 and 0 (TP7-TP0) on a bit-by-bit basis. When the bits enabled for TPC output by NDERA generate the ITU compare match selected in the TPC output control register, the value of the next data register A (NDRA) is automatically transferred to the corresponding PBDR bits and the output value is updated. For disabled bits, there is no transfer and the output value does not change. When reset, NDERA is initialized to H'00. It is not initialized by standby mode.
RENESAS 311
Bit: Bit name: Initial value: R/W:
7 NDER7 0 R/W
6
5
4
3
2 NDER2 0 R/W
1
0
NDER6 NDER5 0 R/W 0 R/W
NDER4 NDER3 0 R/W 0 R/W
NDER1 NDER0 0 R/W 0 R/W
*
Bits 7-0 (next data enable 7-0 (NDER7-NDER0)): NDER7-NDER0 select enable/disable for TPC output groups 1 and 0 (TP7-TP0) in bit units.
Bit 7-0: NDER7-NDER0 Description 0 1 Disables TPC outputs TP7-TP0 (transfer from NDR7-NDR0 to PB7- PB0 is disabled) (initial value) Enables TPC outputs TP7-TP0 (transfer from NDR7-NDR0 to PB7- PB0 is enabled)
11.2.6
Next Data Enable Register B (NDERB)
NDERB is an eight-bit read/write register that enables TPC output groups 3 and 2 (TP15-TP8) on a bit-by-bit basis. When the bits enabled for TPC output by NDERB generate the ITU compare match selected in the TPC output control register, the value of the next data register B (NDRB) is automatically transferred to the corresponding PBDR bits and the output value is updated. For disabled bits, there is no transfer and the output value does not change. When reset, NDERB is initialized to H'00. It is not initialized by standby mode.
Bit: 7 6 5 4 3 2 1 0
Bit name: NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
*
Bits 7-0 (next data enable 15-8 (NDER15-NDER8)): NDER15-NDER8 select enable/disable for TPC output groups 3 and 2 (TP15-TP8) in bit units.
Description Disables TPC outputs TP15-TP8 (transfer from NDR15-NDR8 to PB15-PB8 is disabled) (initial value) Enables TPC outputs TP15-TP8 (transfer from NDR15-NDR8 to PB15-PB8 is enabled)
Bit 7-0: NDER15-NDER8 0 1
312 RENESAS
11.2.7
TPC Output Control Register (TPCR)
TPCR is an eight-bit read/write register that selects output trigger signals for TPC outputs. When reset, TPCR is initialized to H'FF. It is not initialized by standby mode.
Bit: 7 6 5 4 3 2 1 0
Bit name: G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W
*
Bits 7 and 6 (group 3 compare-match select 1 and 0 (G3CMS1 and G3CMS0)): G3CMS1 and G3CMS0 select the compare match that triggers TPC output group 3 (TP15-TP12).
Bit 6: G3CMS0 0 1 Description TPC output group 3 (TP15-TP12) output is triggered by compare-match in ITU channel 0 TPC output group 3 (TP15-TP12) output is triggered by compare-match in ITU channel 1 TPC output group 3 (TP15-TP12) output is triggered by compare-match in ITU channel 2 TPC output group 3 (TP15-TP12) output is triggered by compare-match in ITU channel 3 (initial value)
Bit 7: G3CMS1 0
1
0 1
*
Bits 5 and 4 (group 2 compare-match select 1 and 0 (G2CMS1 and G2CMS0)): G2CMS1 and G2CMS0 select the ITU channel that triggers TPC output group 2 (TP11-TP8).
Bit 4: G2CMS0 0 1 Description TPC output group 2 (TP11-TP18) output is triggered by compare-match in ITU channel 0 TPC output group 2 (TP11-TP18) output is triggered by compare-match in ITU channel 1 TPC output group 2 (TP11-TP18) output is triggered by compare-match in ITU channel 2 TPC output group 2 (TP11-TP18) output is triggered by compare-match in ITU channel 3 (initial value)
Bit 5: G2CMS1 0
1
0 1
RENESAS 313
Bits 3 and 2 (group 1 compare-match select 1 and 0 (G1CMS1 and G1CMS0)): G1CMS1 and G1CMS0 select the ITU channel that triggers TPC output group 1 (TP7-TP4).
Bit 3: G1CMS1 0 Bit 2: G1CMS0 0 1 1 0 1 Description TPC output group 1 (TP7-TP4) output is triggered by compare-match in ITU channel 0 TPC output group 1 (TP7-TP4) output is triggered by compare-match in ITU channel 1 TPC output group 1 (TP7-TP4) output is triggered by compare-match in ITU channel 2 TPC output group 1 (TP7-TP4) output is triggered by compare-match in ITU channel 3 (initial value)
*
Bits 1 and 0 (group 0 compare-match select 1 and 0 (G0CMS1 and G0CMS0)): G0CMS1 and G0CMS0 select the ITU channel that triggers TPC output group 0 (TP3-TP0).
Bit 0: G0CMS0 0 1 Description TPC output group 0 (TP3-TP0) output is triggered by compare-match in ITU channel 0 TPC output group 0 (TP3-TP0) output is triggered by compare-match in ITU channel 1 TPC output group 0 (TP3-TP0) output is triggered by compare-match in ITU channel 2 TPC output group 0 (TP3-TP0) output is triggered by compare-match in ITU channel 3 (initial value)
Bit 1: G0CMS1 0
1
0 1
11.2.8
TPC Output Mode Register (TPMR)
TPMR is an eight-bit read/write register that selects between the TPC's ordinary output and nonoverlap output modes in group units. During non-overlap operation, the output waveform cycle is set in ITU general register B (GRB) for use as the output trigger and a non-overlap period is set in general register A (GRA). The output value then changes on compare matches A and B. For details, see section 11.3.4, TPC Output Non-Overlap Operation. TPMR is initialized to H'F0 on a reset. It is not initialized in standby mode.
Bit: Bit name: Initial value: R/W: 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 2 1 0
G3NOV G2NOV G1NOV G0NOV 0 R/W 0 R/W 0 R/W 0 R/W
314 RENESAS
Bits 7-4 (reserved): These bits always read as 1. The write value should always be 1. * Bit 3 (group 3 non-overlap mode (G3NOV)): G3NOV selects the ordinary or non-overlap mode for TPC output group 3 (TP15-TP12).
Description TPC output group 3 operates normally (output value updated according to compare-match A of the ITU channel selected by TPCR) (initial value) TPC output group 3 operates in non-overlap mode (1 output and 0 output can be performed independently according to compare-match A and B of the ITU channel selected by TPCR)
Bit 3: G3NOV 0
1
*
Bit 2 (group 2 non-overlap mode (G2NOV)): G2NOV selects the ordinary or non-overlap mode for TPC output group 2 (TP11-TP8).
Description TPC output group 2 operates normally (output value updated according to compare-match A of the ITU channel selected by TPCR) (initial value) TPC output group 2 operates in non-overlap mode (1 output and 0 output can be performed independently according to compare-match A and B of the ITU channel selected by TPCR)
Bit 2: G2NOV 0
1
*
Bit 1 (group 1 non-overlap mode (G1NOV)): G1NOV selects the ordinary or non-overlap mode for TPC output group 1 (TP7-TP4).
Description TPC output group 1 operates normally (output value updated according to compare-match A of the ITU channel selected by TPCR) (initial value) TPC output group 1 operates in non-overlap mode (1 output and 0 output can be performed independently according to compare-match A and B of the ITU channel selected by TPCR)
Bit 1: G1NOV 0
1
*
Bit 0 (group 0 non-overlap mode (G0NOV)): G0NOV selects the ordinary or non-overlap mode for TPC output group 0 (TP3-TP0).
RENESAS 315
Bit 0: G0NOV 0
Description TPC output group 0 operates normally (output value updated according to compare-match A of the ITU channel selected by TPCR) (initial value) TPC output group 0 operates in non-overlap mode (1 output and 0 output can be performed independently according to compare-match A and B of the ITU channel selected by TPCR)
1
11.3
11.3.1
Operation
Overview
When corresponding bits in the PBCR1, PBCR2, NDERA and NDERB registers are set to 1, TPC output is enabled and the PBDR data register values are output. After that, when the comparematch event selected by TPCR occurs, the next data register contents (NDRA and NDRB) are transferred to the PBDR and output values are updated. Figure 11.2 illustrates the TPC output operation.
CR Q
NDER Q Output trigger signal
C Port function select TPC output pin Q DR D Q NDR D Internal data bus
Figure 11.2 TPC Output Operation If new data is written in next data registers A and B before the next compare-match occurs, a maximum 16 bits of data can be output at each successive compare-match. See section 11.3.4, TPC Output Non-Overlap Operation, for details on non-overlap operation.
316 RENESAS
11.3.2
Output Timing
If TPC output is enabled, next data register (NDRA/NDRB) contents are transferred to the data register (PBDR) and output when the selected compare-match occurs. Figure 11.3 shows the timing of these operations. The example is of ordinary output upon compare match A with groups 2 and 3.
CK
TCNT
N
N+1
GRA Compare match A signal NDRB
N
n
PBDR
m
n
TP15-TP8
m
n
Figure 11.3 Transfer and Output Timing for NDR Data 11.3.3 Examples of Use of Ordinary TPC Output
Settings for Ordinary TPC Output (figure 11.4): 1. Select GRA as the output compare register (output disable) with the timer I/O control register (TIOR). 2. Set the TPC output trigger cycle. 3. Select the counter clock with the TPSC2-TPSC0 bits of the timer control register (TCR). Select the counter clear sources with the CCLR1 and CCLR0 bits. 4. Set the timer interrupt enable register (TIER) to enable IMIA interrupts. Transfers to the NDR can also be set using the DMAC. 5. Set the initial output value in the I/O port data register to be used by TPC. 6. Set the I/O port control register to be used by TPC as the TP pin function (11).
RENESAS 317
7. Set to 1 the bit that performs TPC output to the next data enable register (NDER). 8. Select the ITU compare match that will be the TPC output trigger using the TPC output control register (TPCR). 9. Set the next TPC output value in the NDR. 10. Set 1 in the STR bit of the timer start register (TSTR) and start the timer counter counting. 11. Set the next output value in the NDR whenever an IMIA interrupt is generated.
Original TPC output operation Select GR function Set GRA ITU setting Set count operation Select interrupt request Set initial output value Set port output Port and TPC setting Set TPC output enable Select TPC output trigger Set next TPC output value ITU setting Start count (3) (1) (2)
(4) (5) (6)
(7) (8) (9) (10)
Compare match? Yes
No
Set next TPC output value (11)
Figure 11.4 Example of Setting Procedure for TPC Ordinary Output
318 RENESAS
Five-Phase Pulse Output (figure 11.5): 1. Set the GRA of the ITU that serves as output trigger as the output compare register. Set the cycle time in the GRA of the ITU and select to clear the counter upon compare match A. Set the IMIEA bit of TIER to 1 to enable the compare match A interrupt. 2. Write H'FFC0 in the PBCR1, write H'F8 in the NDERB, and set G3CMS0, G3CMS1, G2CMS1 and G2CMS0 in the TPCR to set the ITU compare match selected in step 1 as the output trigger. Write output data H'80 in the NDRB. 3. When the selected ITU channel starts operating and a compare-match occurs, the values in the NDRB are transferred to the PBDR and output. The compare-match/input capture A (IMIA) interrupt service routine writes the next output data (H'C0) in the NDRB. 4. Five-phase pulse output can be obtained by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive compare-match interrupts. If the DMA controller is set for activation by compare-match, pulse output can be obtained without loading the CPU.
TCNT value TCNT GRA
Compare matches
H'0000 NDRB PBDR TP15 TP14 TP13 TP12 TP11
80 C0 40 60 20 30 10 18 08 88 80 C0
Time
8000 C000 4000 6000 2000 3000 1000 1800 0800 8800 8000 C000
Figure 11.5 TPC Output Example (5-Phase Pulse Output)
RENESAS 319
11.3.4
TPC Output Non-Overlap Operation
Setting Procedures for TPC Output Non-Overlap Operation (figure 11.6): 1. Select GRA and GRB as output compare registers (output disable) with the timer I/O control register (TIOR). 2. Set the TPC output trigger cycle to GRB and the non-overlap cycle to GRA. 3. Select the counter clock with the TPSC2-TPSC0 bits of the timer control register (TCR). Select the counter clear sources with the CCLR1 and CCLR0 bits. 4. Set the timer interrupt enable register (TIER) to enable IMIA interrupts. Transfers to the NDR can also be set using the DMAC. 5. Set the initial output value in the I/O port data register to be used by TPC. 6. Set the I/O port control register to be used by TPC as the TP pin function (11). 7. Set to 1 the bit that performs TPC output to the next data enable register (NDER). 8. Select the ITU compare match that will be the TPC output trigger using the TPC output control register (TPCR). 9. Select the group that performs the non-overlap operation in the TPC output mode register (TPMR). 10. Set the next TPC output value in the NDR. 11. Set 1 in the STR bit of the timer start register (TSTR) and start the timer counter counting. 12. Set the next output value in the NDR whenever an IMIA interrupt is generated.
320 RENESAS
TPC output nonoverlap operation Select GR function Set GRA ITU setting Set count operation Select interrupt request Set initial output value Set TPC output Set TPC transfer enable Port and TPC setting Select TPC output trigger Select non-overlap group Set next TPC output value Start count (3) (4) (5) (6) (7) (8) (9) (10) (11) (1) (2)
ITU setting
Compare match A?
No
Yes Set next TPC output value
(12)
Figure 11.6 Example of Setting Procedures for TPC Output Non-Overlap Operation
RENESAS 321
TPC Output Non-Overlap Operation (Four-Phase Complementary Non-Overlap Output) (figure 11.7): 1. Set GRA and GRB of the ITU that serves as output trigger in the output compare registers. Set the cycle in the GRB and the non-overlap cycle time in the GRA and select to clear the counter upon compare match B. Set the IMIEA bit of TIER to 1 to enable the IMIA interrupt. 2. Write H'FFFF in the PBCR1, write H'FF in the NDERB, and set G3CMS1, G3CMS0, G2CMS1 and G2CMS0 in the TPCR to set the ITU compare match selected in step 1 as the output trigger. Set the G3NOV and G2NOV bits in the TPMR to 1 to set the non-overlap operation. Write output data H'95 in the NDRB. 3. When the selected ITU channel starts operating and a GRB compare-match occurs, 1 output changes to 0 output; when a GRA compare match occurs, 0 output changes to 1 output. (The change from 0 output to 1 output is delayed by the value set in GRA.) The IMIA interrupt service routine writes the next output data (H'65) in the NDRB. 4. Four-phase complementary non-overlap output can be obtained by writing H'59, H'56, H'95... at successive IMIA interrupts. If the DMA controller is set for activation by compare-match, pulse output can be obtained without loading the CPU.
322 RENESAS
TCNT value GRB GRA H'0000 NDRB PBDR 95 00 95 65 05 65 59 41 59 56 50 56 95 14 95 65 05 65 Time TCNT
Non-overlap cycle TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8
Figure 11.7 Non-Overlap Output Example (Four-Phase Complementary Output)
RENESAS 323
11.3.5
TPC Output by Input Capture
TPC can also be output by using input capture rather than ITU compare matches. The general register A (GRA) of the ITU selected by the TPCR functions as an input capture register and TPC output occurs upon an input capture signal. Figure 11.8 shows the timing.
CK TIOC pin Input capture signal NDR DR M N N
Figure 11.8 TPC Output by Input Capture
324 RENESAS
11.4
11.4.1
Usage Notes
Non-Overlap Operation
During non-overlap operation, transfers from the NDR to data registers (DR) occurs as follows. 1. NDR contents are always transferred to the DR on compare match A. 2. The contents of the bit transferred by the NDR are only transferred on compare match B when they are 0. No transfer occurs for a 1. Figure 11.9 illustrates the TPC output operation during non-overlap.
CR Q
NDER Q Compare match A Compare match B
C Port function select TPC output pin Q DR D Q NDR D
Figure 11.9 TPC Output Non-Overlap Operation
RENESAS 325
When a compare match B occurs before the compare match A, the 0 data transfer can be performed before the 1 data transfer, so a non-overlapping waveform can be output. In such cases, be sure not to change the NDR contents until the compare match A after the compare match B occurs (non-overlap period). This can be ensured by writing the next data to the NDR using the IMIA interrupt service routine. The DMAC can also be started up using an IMIA interrupt. However, these write operations should be performed prior to the next compare match B. The timing is shown in figure 11.10.
Compare match A Compare match B NDR write NDR NDR write
DR 0 output 0/1 output NDR write period NDR write disable period 0 output 0/1 output NDR write period NDR write disable period
Figure 11.10 Non-Overlap Operation and NDR Write Timing
326 RENESAS
Section 12 Watchdog Timer (WDT)
12.1 Overview
The SuperH microcomputer has a one-channel watchdog timer (WDT) for monitoring system operations. If a system becomes uncontrolled and the timer counter overflows without being rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally . The WDT can simultaneously generate an internal reset signal for the entire chip. When this watchdog function is not needed, the WDT can be used as an interval timer. In the interval timer operation, an interval timer interrupt is generated at each counter overflow. The WDT is also used in recovering from the standby mode. 12.1.1 * * Features
* * *
Watchdog timer mode and interval timer mode can be selected. Outputs WDTOVF in the watchdog timer mode. When the counter overflows in the watchdog timer mode, overflow signal WDTOVF is output externally. You can select whether or not to reset the chip internally when this happens. Either the power-on reset or manual reset signal can be selected as the internal reset signal. Generates interrupts in the interval timer mode. When the counter overflows, it generates an interval timer interrupt. Used to clear the standby mode. Selection of eight counter clock sources
RENESAS 327
12.1.2
Block Diagram
Figure 12.1 is the block diagram of the WDT.
ITI (interrupt signal)
Overflow Interrupt control Clock Clock select
WDTOVF Internal reset signal*
Reset control
/2 /64 /128 /256 /512 /1024 /4096 /8192 Internal clock sources Internal data bus
RSTCSR
TCNT
TCSR
Module bus WDT
Bus interface
TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register Note: The internal reset signal can be generated by setting the register. The type of reset can be selected (power-on or manual resets).
Figure 12.1 WDT Block Diagram 12.1.3 Pin Configuration
Table 12.1 shows the pin configuration.
RENESAS 328
Table 12.1 Pin Configuration
Pin Watchdog timer overflow Abbreviation WDTOVF I/O O Function Outputs the counter overflow signal in the watchdog mode
12.1.4
Register Configuration
Table 12.2 summarizes the three WDT registers. They are used to select the clock, switch the WDT mode, and control the reset signal. Table 12.2 WDT Registers
Address Name Timer control/status register Timer counter Reset control/status register Abbreviation TCSR R/W R/(W)*3 Initial Value H'18 Write*1 H'5FFFFB8 Read* 2 H'5FFFFB8
TCNT RSTCSR
R/W R/(W)*3
H'00 H'3F H'5FFFFBA
H'5FFFFB9 H'5FFFFBB
Notes: 1. Write by word transfer. It cannot be written in byte or long word. 2. Read by byte transfer. It cannot be read in word or long word. 3. Only 0 can be written in bit 7 to clear the flag.
12.2
12.2.1
Register Descriptions
Timer Counter (TCNT)
The TCNT is an eight-bit readable and writable upcounter. The TCNT differs from other registers in that it is more difficult to write. See section 12.2.4, Register Access, for details. When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2-0 (CKS2-CKS0) in the TCSR. When the value of the TCNT overflows (changes from H'FF-H'00), a watchdog timer overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit of the TCSR. The TCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0. It is not initialized in the standby mode.
RENESAS 329
Bit: Bit name: Initial value: R/W:
7
6
5
4
3
2
1
0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
12.2.2
Timer Control/Status Register (TCSR)
The timer control/status register (TCSR) is an eight-bit readable and writable register. The TCSR differs from other registers in being more difficult to write. See section 12.2.4, Register Access, for details. Its functions include selecting the timer mode and clock source. Bits 7-5 are initialized to 000 by a reset or in standby mode. Bits 2-0 are initialized to 000 by a reset, but retain their values in the standby mode.
Bit: Bit name: Initial value: R/W: 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
*
Bit 7 (overflow flag (OVF)): OVF indicates that the TCNT has overflowed from H'FF-H'00. It is not set in the watchdog timer mode.
Description No overflow of TCNT in interval timer mode (initial value) Cleared by reading OVF, then writing 0 in OVF
Bit 7: OVF 0
1
TCNT overflow in the interval timer mode
*
Bit 6 (timer mode select (WT/IT)): WT/IT selects whether to use the WDT as a watchdog timer or interval timer. When the TCNT overflows, the WDT either generates an interval timer interrupt (ITI) or generates a WDTOVF signal, depending on the mode selected.
Description Interval timer mode: interval timer interrupt to the CPU when TCNT overflows (initial value) Watchdog timer mode: WDTOVF signal output externally when TCNT overflows. Section 12.2.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when TCNT overflows in the watchdog timer mode.
Bit 6: WT/IT 0 1
*
Bit 5 (timer enable (TME)): TME enables or disables the timer.
RENESAS 330
Bit 5: TME 0 1
Description Timer disabled: TCNT is initialized to H'00 and count-up stops (initial value) Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is generated when TCNT overflows.
* *
Bits 4 and 3 (reserved): These bits always read as 1. The write value should always be 1. Bits 2-0 (clock Select 2-0 (CKS2-CKS0)): CKS2-CKS0 select one of eight internal clock sources for input to the TCNT. The clock signals are obtained by dividing the frequency of the system clock ().
Description
Bit 2: CKS2 0 0 0 0 1 1 1 1
Bit 1: CKS1 0 0 1 1 0 0 1 1
Bit 0: CKS0 0 1 0 1 0 1 0 1
Clock Source /2 (initial value) /64 /128 /256 /512 /1024 /4096 /8192
Overflow Interval* ( = 20 MHz) 25.6 s 819.2 s 1.6 ms 3.3 ms 6.6 ms 13.1 ms 52.4 ms 104.9 ms
Note: The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs.
12.2.3
Reset Control/Status Register (RSTCSR)
The RSTCSR is an eight-bit readable and writable register that controls output of the reset signal generated by timer counter (TCNT) overflow and selects the internal reset signal type. The RSTCSR differs from other registers in that it is more difficult to write. See section 12.2.4 Register Access, for details. RSTCR is initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by the internal reset signal generated by the overflow of the WDT. It is initialized to H'1F in standby mode.
Bit: Bit name: Initial value: R/W: 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
Note: Only 0 can be written in bit 7 to clear the flag.
RENESAS 331
*
Bit 7 (watchdog timer overflow (WOVF)): WOVF indicates that the TCNT has overflowed (H'FF H'00) in the watchdog timer mode. It is not set in the interval timer mode.
Description No TCNT overflow in watchdog timer mode (initial value) Cleared when software reads WOVF, then writes 0 in WOVF
Bit 7: WOVF 0
1
Set by TCNT overflow in watchdog timer mode
*
Bit 6 (reset enable (RSTE)): RSTE selects whether to reset the chip internally if the TCNT overflows in the watchdog timer mode.
Description Not reset when TCNT overflows (initial value). LSI not reset internally, but TCNT and TCSR reset within WDT. Reset when TCNT overflows
Bit 6: RSTE 0 1
*
Bit 5 (reset select (RSTS)): RSTS selects the type of internal reset generated if the TCNT overflows in the watchdog timer mode.
Description Power-on reset initial value) Manual reset
Bit 5: RSTS 0 1
*
Bits 4-0 (reserved): These bits always read as 1. The write value should always be 1.
RENESAS 332
12.2.4
Register Access
The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in that they are more difficult to write. The procedures for writing and reading these registers are given below. Writing to the TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte transfer instructions. The TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must be H'5A (for the TCNT) or H'A5 (for the TCSR) (figure 12.2). This transfers the write data from the lower byte to the TCNT or TCSR.
Writing to the TCNT 15 Address: H'5FFFFB8 H'5A 8 7 0
Write data
Writing to the TCSR 15 Address: H'5FFFFB8 H'A5 8 7 0
Write data
Figure 12.2 Writing to the TCNT and TCSR
RENESAS 333
Writing to the RSTCSR: The RSTCSR must be written by a word access to address H'5FFFFFBA. It cannot be written by byte transfer instructions. Procedures for writing 0 in WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 12.3. To write 0 in the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected.
Writing 0 to the WOVF bit 15 Address: H'5FFFFBA H'A5 8 7 H'00 0
Writing to the RSTE and RSTS bits 15 Address: H'5FFFFBA H'5A 8 7 0
Write data
Figure 12.3 Writing to the RSTCSR Reading from the TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'5FFFFB8 for the TCSR, H'5FFFFB9 for the TCNT, and H'5FFFFBB for the RSTCSR.
12.3
12.3.1
Operation
Operation in the Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT and TME bits of the TCSR to 1. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. If the TCNT fails to be rewritten and overflows due to a system crash or the like, a WDTOVF signal is output (figure 12.4). The WDTOVF signal can be used to reset external system devices. The WDTOVF signal is output for 128 clock cycles. If the RSTE bit in the RSTCSR is set to 1, a signal to reset the chip will be generated internally simultaneous to the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual reset can be selected by the RSTS bit. The internal reset signal is output for 512 clock cycles. When a watchdog reset is generated simultaneously with input at the RES pin, the software distinguishes the RES reset from the watchdog reset by checking the WOVF bit in the RSTCSR. The RES reset takes priority. The WOVF bit is cleared to 0.
RENESAS 334
TCNT value Overflow H'FF
H'00 WT/IT = 1 TME = 1 H'00 written in TCNT WOVF = 1
Time WT/IT = 1 H'00 written TME = 1 in TCNT
WDTOVF and internal reset generated WDTOVF signal 128 clock Internal reset signal* 512 clock WT/IT: Timer mode select bit TME: Timer enable bit Note: The internal reset signal is only generated when the RSTE bit is 1.
Figure 12.4 Operation in the Watchdog Timer Mode
RENESAS 335
12.3.2
Operation in the Interval Timer Mode
To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1. An interval timer interrupt (ITI) is generated each time the timer counter overflows. This function can be used to generate interval timer interrupts at regular intervals (figure 12.5).
TCNT value H'FF Overflow Overflow Overflow Overflow
H'00 WT/IT = 0 TME = 1 ITI ITI ITI ITI
Time
Figure 12.5 Operation in the Interval Timer Mode 12.3.3 Operation in the Standby Mode
The watchdog timer has a special function to clear the standby mode with an NMI interrupt. When using the standby mode, set the WDT as described below. Transition to the Standby Mode: The TME bit in the TCSR must be cleared to 0 to stop the watchdog timer counter before it enters the standby mode. The chip cannot enter the standby mode while the TME bit is set to 1. Set bits CKS2-CKS0 so that the counter overflow interval is equal to or longer than the oscillation settling time. See section 20.3, AC Characteristics, for the oscillation settling time. Recovery from the Standby Mode: When an NMI request signal is received in standby mode, the clock oscillator starts running and the watchdog timer starts counting at the rate selected by bits CKS2-CKS0 before the standby mode was entered. When the TCNT overflows (changes from H'FF-H'00), the system clock () is presumed to be stable and usable; clock signals are supplied to the entire chip and the standby mode ends. For details on the standby mode, see section 19, Power Down States.
RENESAS 336
12.3.4
Timing of Setting the Overflow Flag (OVF)
In the interval timer mode, when the TCNT overflows the OVF flag is set to 1 and an interval timer interrupt is requested (figure 12.6).
CK
TCNT
H'FF
H'00
Overflow signal (internal signal)
OVF
Figure 12.6 Timing of Setting the OVF 12.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
When the TCNT overflows the WOVF bit of the RSTCSR is set to 1 and a WDTOVF signal is output. When the RSTE bit is set to 1, TCNT overflow enables an internal reset signal to be generated for the entire chip (figure 12.7).
CK
TCNT
H'FF
H'00
Overflow signal (internal signal)
WOVF
Figure 12.7 Timing of Setting the WOVF Bit and Internal Reset
RENESAS 337
12.4
12.4.1
Usage Notes
TCNT Write and Count Up Contention
If a timer counter clock pulse is generated during the T3 state of a write cycle to the TCNT, the write takes priority and the timer counter is not incremented (figure 12.8).
TCNT write cycle T1 CK Address Internal write signal TCNT address T2 T3
TCNT input clock
TCNT N M Counter write data
Figure 12.8 Contention between TCNT Write and Increment 12.4.2 Changing CKS2-CKS0 Bit Values
If the values of bits CKS2-CKS0 are altered while the WDT is running, the count may increment incorrectly. Always stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2-CKS0. 12.4.3 Changing Watchdog Timer/Interval Timer Modes
To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between interval timer mode and watchdog timer mode.
RENESAS 338
12.4.4
System Reset With WDTOVF
If a WDTOVF signal is input to the RES pin, the LSI cannot initialize correctly. Avoid logical input of the WDTOVF output signal to the RES input pin. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 12.9.
SuperH microprocessor Reset input RES
Reset signal to entire system
WDTOVF
Figure 12.9 Example of a System Reset Circuit with a WDTOVF Signal 12.4.5 Internal Reset With the Watchdog Timer
If the RSTE bit is cleared to 0 in the watchdog timer mode, the LSI will not reset internally when a TCNT overflow occurs, but the TCNT and TCSR in WDT will reset.
RENESAS 339
Section 13 Serial Communication Interface (SCI)
13.1 Overview
The SuperH microcomputer has a serial communication interface (SCI) with two independent channels. Both channels are functionally identical. The SCI supports both asynchronous and clocked synchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. 13.1.1 * Features
*
*
* * *
Asynchronous mode Serial data communications are synched by start-stop in character units. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other chip that employs a standard asynchronous serial communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data communication formats. Data length: seven or eight bits Stop bit length: one or two bits Parity: even, odd, or none Multiprocessor bit: one or none Receive error detection: parity, overrun, and framing errors Break detection: by reading the RxD level directly when a framing error occurs Clocked synchronous mode Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a clocked synchronous communication function. There is one serial data communication format. Data length: eight bits Receive error detection: overrun errors Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. On-chip baud rate generator with selectable bit rates Internal or external transmit/receive clock source: baud rate generator (internal) or SCK pin (external) Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receiveerror interrupts are requested independently. The transmit-data-empty and receive-data-full interrupts can start the direct memory access controller (DMAC) to transfer data.
RENESAS 341
13.1.2
Block Diagram
Figure 13.1 shows a block diagram of the SCI.
Bus interface
Module data bus
Internal data bus
RDR
TDR
SSR SCR
BRR /4 /16 /64
RXD
RSR
TSR
SMR Transmit/ receive control
Baud rate generator
TXD
Parity generation Parity check
Clock External clock TEI TXI RXI ERI
SCK
SCI RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register
Figure 13.1 SCI Block Diagram
RENESAS 342
13.1.3
Input/Output Pins
Table 13.1 summarizes the SCI pins by channel. Table 13.1 SCI Pins
Channel 0 Pin Name Serial clock pin Receive data pin Transmit data pin 1 Serial clock pin Receive data pin Transmit data pin Abbreviation SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 Input/Output Input/output Input Output Input/output Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output
13.1.4
Register Configuration
Table 13.2 summarizes the SCI internal registers. These registers select the communication mode (asynchronous or clocked synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. Table 13.2 Registers
Channel 0 Address* 1 H'05FFFEC0 H'05FFFEC1 H'05FFFEC2 H'05FFFEC3 H'05FFFEC4 H'05FFFEC5 1 H'05FFFEC8 H'05FFFEC9 Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Serial mode register Bit rate register Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 R/W R/W R/W R/W R/W R/(W)*2 R R/W R/W R/W R/W R/(W)*2 R Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'00 H'FF H'00 H'FF H'84 H'00 Access size 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16
H'05FFFECA Serial control register H'05FFFECB Transmit data register H'05FFFECC Serial status register H'05FFFECD Receive data register
Notes: 1. Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Description of Areas. 2. Write 0 to clear flags.
RENESAS 343
13.2
13.2.1
Register Descriptions
Receive Shift Register
The receive shift register (RSR) receives serial data. Data input at the RxD pin are loaded into the RSR in the order received, LSB (bit 0) first. In this way the SCI converts received data to parallel form. When one byte has been received, it is automatically transferred to the receive data register (RDR). The CPU cannot read or write the RSR directly.
Bit: Bit name: R/W: -- -- -- -- -- -- -- -- 7 6 5 4 3 2 1 0
13.2.2
Receive Data Register
The receive data register (RDR) stores serial receive data. The SCI completes the reception of one byte of serial data by moving the received data from the receive shift register (RSR) into the RDR for storage. The RSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously. The CPU can read but not write the RDR. The RDR is initialized to H'00 by a reset or in standby mode.
Bit: Bit name: Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0
13.2.3
Transmit Shift Register
The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the transmit data register (TDR) into the TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from the TDR into the TSR and starts transmitting again. If the TDRE bit of the SSR is 1, however, the SCI does not load the TDR contents into the TSR. The CPU cannot read or write the TSR directly.
Bit: Bit name: R/W: -- -- -- -- -- -- -- -- 7 6 5 4 3 2 1 0
RENESAS 344
13.2.4
Transmit Data Register
The transmit data register (TDR) is an eight-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in the TDR into the TSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in the TDR during serial transmission from the TSR. The CPU can always read and write the TDR. The TDR is initialized to H'FF by a reset or in standby mode.
Bit: Bit name: Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 7 6 5 4 3 2 1 0
13.2.5
Serial Mode Register
The serial mode register (SMR) is an eight-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write the SMR. The SMR is initialized to H'00 by a reset or in standby mode.
Bit: Bit name: Initial value: R/W: 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
*
Bit 7 (communication mode (C/A)): C/A selects whether the SCI operates in the asynchronous or clocked synchronous mode.
Description Synchronous mode (initial value) Clocked synchronous mode
Bit 7: C/A 0 1
RENESAS 345
*
Bit 6 (character length (CHR)): CHR selects seven-bit or eight-bit data in the asynchronous mode. In the clocked synchronous mode, the data length is always eight bits, regardless of the CHR setting.
Description Eight-bit data (initial value) Seven-bit data. When seven-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted.
Bit 6: CHR 0 1
*
Bit 5 (parity enable (PE)): PE selects whether to add a parity bit to transmit data and check the parity of receive data, in the asynchronous mode. In the clocked synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting.
Description Parity bit not added or checked (initial value) Parity bit added and checked. When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting.
Bit 5: PE 0 1
*
Bit 4 (parity mode (O/E): O/E selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and check. The O/E setting is ignored in the clocked synchronous mode, or in the asynchronous mode when parity addition and check is disabled.
Description Even parity. If even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. Receive data must have an even number of 1s in the received character and parity bit combined (initial value). Odd parity. If odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. Receive data must have an odd number of 1s in the received character and parity bit combined.
Bit 4: O/E 0
1
RENESAS 346
*
Bit 3 (stop bit length (STOP)): STOP selects one or two bits as the stop bit length in the asynchronous mode. This setting is used only in the asynchronous mode. It is ignored in the clocked synchronous mode because no stop bits are added. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit. If the second stop bit is 0, it is treated as the start bit of the next incoming character.
Bit 3: STOP 0 1
Description One stop bit. In transmitting, a single bit of 1 is added at the end of each transmitted character (initial value). Two stop bits. In transmitting, two bits of 1 are added at the end of each transmitted character.
*
Bit 2 (multiprocessor mode (MP)): MP selects multiprocessor format. When multiprocessor format is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The MP bit setting is used only in the asynchronous mode; it is ignored in the clocked synchronous mode. For the multiprocessor communication function, see section 13.3.3, Multiprocessor Communication.
Description Multiprocessor function disabled (initial value) Multiprocessor format selected
Bit 2: MP 0 1
*
Bits 1 and 0 (clock select 1 and 0 (CKS1 and CKS0)): CKS1 and CKS0 select the internal clock source of the on-chip baud rate generator. Four clock sources are available: , /4, /16, and /64. For further information on the clock source, bit rate register settings, and baud rate, see section 13.2.8, Bit Rate Register.
Bit 0: CKS0 0 1 Description System clock () (initial value) /4 /16 /64
Bit 1: CKS1 0
1
0 1
RENESAS 347
13.2.6
Serial Control Register
The serial control register (SCR) enables the SCI transmitter/receiver, selects serial clock output in the asynchronous mode, enables and disables interrupts, and selects the transmit/receive clock source. The CPU can always read and write the SCR. The SCR is initialized to H'00 by a reset or in standby mode.
Bit: Bit name: Initial value: R/W: 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W
*
Bit 7 (transmit interrupt enable (TIE)): TIE enables or disables the transmit-data-empty interrupt (TXI) requested when the transmit data register empty bit (TDRE) in the serial status register (SSR) is set to 1 due to transfer of serial transmit data from the TDR to the TSR.
Description Transmit-data-empty interrupt request (TXI) is disable. The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing TDRE to 0, or by clearing TIE to 0 (initial value). Transmit-data-empty interrupt request (TXI) is enabled
Bit 7: TIE 0
1
*
Bit 6 (receive interrupt enable (RIE)): RIE enables or disables the receive-data-full interrupt (RXI) requested when the receive data register full bit (RDRF) in the serial status register (SSR) is set to 1 due to transfer of serial receive data from the RSR to the RDR. Also enables or disables receive-error interrupt (ERI) requests.
Description Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled. RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0 (initial value). Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled
Bit 6: RIE 0
1
RENESAS 348
Bit 5 (transmit enable (TE)): TE enables or disables the SCI transmitter.
Bit 5: TE 0 1 Description Transmitter disabled. The transmit data register empty bit (TDRE) in the serial status register (SSR) is locked at 1 (initial value). Transmitter enabled. Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SSR) is cleared to 0 after writing of transmit data into the TDR. Select the transmit format in the SMR before setting TE to 1.
*
Bit 4 (receive enable (RE)): RE enables or disables the SCI receiver.
Description Receiver disabled (initial value). Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags retain their previous values. Receiver enabled. Serial reception starts when a start bit is detected in the asynchronous mode, or serial clock input is detected in the clocked synchronous mode. Select the receive format in the SMR before setting RE to 1.
Bit 4: RE 0
1
*
Bit 3 (multiprocessor interrupt enable (MPIE)): MPIE enables or disables multiprocessor interrupts. The MPIE setting is used only in the asynchronous mode, and only if the multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1 during reception. The MPIE setting is ignored in the clocked synchronous mode or when the MP bit is cleared to 0.
Description Multiprocessor interrupts are disabled (normal receive operation) (initial value) MPE is cleared to 0 when: 1. MPIE is cleared to 0, or 2. Multiprocessor bit (MPB) is set to 1 in receive data.
Bit 3: MPIE 0
1
Multiprocessor interrupts are enabled: Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the serial status register (SSR) are disabled until the multiprocessor bit is set to 1. The SCI does not transfer receive data from the RSR to the RDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in the serial status register (SSR). When it receives data that includes MPB = 1, MPB is set to 1, and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in the SCR are set to 1), and allows the FER and ORER to be set. RENESAS 349
*
Bit 2 (transmit-end interrupt enable (TEIE)): TEIE enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain new transmit data when the MSB is transmitted.
Description Transmit-end interrupt (TEI) requests are disabled* (initial value) The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR) after it has been set to 1, then clearing TDRE to 0; by clearing the transmit end (TEND) bit to 0; or by clearing the TEIE bit to 0.
Bit 2: TEIE 0
1
Transmit-end interrupt (TEI) requests are enabled.
*
Bits 1 and 0 (clock enable 1 and 0 (CKE1 and CKE0)): CKE1 and CKE0 select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for general-purpose input/output, serial clock output, or serial clock input. The CKE0 setting is valid only in the asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0). The CKE0 setting is ignored in the clocked synchronous mode, or when an external clock source is selected (CKE1 = 1). Select the SCI operating mode in the serial mode register (SMR) before setting CKE1 and CKE0. For further details on selection of the SCI clock source, see table 13.9 in section 13.3, Operation.
Bit 1: CKE1 0
Bit 0: CKE0 0
Description*1 Synchronous mode Internal clock, SCK pin used for input pin (input signal is ignored or output pin output level is undefined) Internal clock, SCK pin used for clock output*3 External clock, SCK pin used for clock input* 4 External clock, SCK pin used for clock input* 4
Clocked synchronous mode Internal clock, SCK pin used for serial clock output*2 0 1 Synchronous mode
Clocked synchronous mode Internal clock, SCK pin used for serial clock output 1 0 Synchronous mode
Clocked synchronous mode External clock, SCK pin used for serial clock input 1 1 Synchronous mode
Clocked synchronous mode External clock, SCK pin used for serial clock input Notes: 1. The SCK pin is multiplexed with other functions. Set the pin function controller (PFC) to select the SCK function and the SCK input/output of the SCK pin. 2. Initial value 3. The output clock frequency is the same as the bit rate. 4. The input clock frequency is 16 times the bit rate.
RENESAS 350
13.2.7
Serial Status Register
The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI operating status. The CPU can always read and write the SSR, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. The SSR is initialized to H'84 by a reset or in standby mode.
Bit: Bit name: Initial value: R/W: 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W
Note: Write 0 to clear flag.
*
Bit 7 (transmit data register empty (TDRE)): TDRE indicates that the SCI has loaded transmit data from the TDR into the TSR and serial transmit new data can be written in the TDR.
Description TDR contains valid transmit data TDRE is cleared to 0 when: * Software reads TDRE after it has been set to 1, then writes 0 in TDRE * The DMAC writes data in TDR
Bit 7: TDRE 0
1
TDR does not contain valid transmit data (initial value) TDRE is set to 1 when: * The chip is reset or enters standby mode * The TE bit in the serial control register (SCR) is cleared to 0 * TDR contents are loaded into TSR, so new data can be written in TDR
RENESAS 351
*
Bit 6 (receive data register full (RDRF)): RDRF indicates that RDR contains received data.
Description RDR does not contain valid received data (initial value) RDRF is cleared to 0 when: * The chip is reset or enters standby mode * Software reads RDRF after it has been set to 1, then writes 0 in RDRF * The DMAC reads data from RDR
Bit 6: RDRF 0
1
RDR contains valid received data. RDRF is set to 1 when serial data is received normally and transferred from RSR to RDR.
Note: The RDR and RDRF are not affected by detection of receive errors or by clearing of the RE bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER) occurs and the received data is lost.
*
Bit 5 (overrun error (ORER)): Indicates that data reception ended abnormally due to an overrun error.
Description Receiving is in progress or has ended normally (initial value)* 1 ORER is cleared to 0 when: * The chip is reset or enters standby mode * Software reads ORER after it has been set to 1, then writes 0 in ORER A receive overrun error occurred*2 ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1
Bit 5: ORER 0
1
Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which retains its previous value. 2. RDR continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. In the clocked synchronous mode, serial transmitting is disabled.
RENESAS 352
*
Bit 4 (framing error (FER)): FER indicates that data reception ended abnormally due to a framing error in the asynchronous mode.
Description Receiving is in progress or has ended normally. Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which retains its previous value (initial value). FER is cleared to 0 when: * The chip is reset or enters standby mode * Software reads FER after it has been set to 1, then writes 0 in FER
Bit 4: FER 0
1
A receive framing error occurred. When the stop bit length is two bits, only the first bit is checked. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into the RDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In the clocked synchronous mode, serial transmitting is also disabled. FER is set to 1 if the stop bit at the end of receive data is checked and found to be 0.
*
Bit 3 (parity error (PER)): PER indicates that data reception (with parity) ended abnormally due to a parity error in the asynchronous mode.
Description Receiving is in progress or has ended normally. Clearing the RE bit to 0 in the serial control register does not affect the PER bit, which retains its previous value (initial value). PER is cleared to 0 when: * The chip is reset or enters standby mode * Software reads PER after it has been set to 1, then writes 0 in PER
Bit 3: PER 0
1
A receive parity error occurred. When a parity error occurs, the SCI transfers the receive data into the RDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. In the clocked synchronous mode, serial transmitting is also disabled. PER is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SMR).
RENESAS 353
*
Bit 2 (transmit end (TEND)): TEND indicates that when the last bit of a serial character was transmitted, the TDR did not contain new transmit data, so transmission has ended. TEND is a read-only bit and cannot be written.
Description Transmission is in progress TEND is cleared to 0 when: * Software reads TDRE after it has been set to 1, then writing 0 in TDRE * The DMAC writes data in TDR
Bit 2: TEND 0
1
End of transmission (initial value) TEND is set to 1 when: * The chip is reset or enters standby mode * TE is cleared to 0 in the serial control register (SCR) * TDRE is 1 when the last bit of a one-byte serial character is transmitted
*
Bit 1 (multiprocessor bit (MPB)): MPB stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in the asynchronous mode. The MPB is a read-only bit and cannot be written.
Description Multiprocessor bit value in receive data is 0. If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its previous value (initial value). Multiprocessor bit value in receive data is 1
Bit 1: MPB 0
1
*
Bit 0 (multiprocessor bit transfer (MPBT)): MPBT stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in the asynchronous mode. The MPBT setting is ignored in the clocked synchronous mode, when a multiprocessor format is not selected, or when the SCI is not transmitting.
Description Multiprocessor bit value in transmit data is 0 (initial value) Multiprocessor bit value in transmit data is 1
Bit 0: MPBT 0 1
RENESAS 354
13.2.8
Bit Rate Register (BRR)
The bit rate register (BRR) is an eight-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the serial transmit/receive bit rate. The CPU can always read and write the BRR. The BRR is initialized to H'FF by a reset or in standby mode. SCI1 and SCI2 have independent baud rate generator control, so different values can be set in the two channels.
Bit: Bit name: Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 7 6 5 4 3 2 1 0
Table 13.3 shows examples of BRR settings in the asynchronous mode; table 13.4 shows examples of BBR settings in the clocked synchronous mode. Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode
(MHz) 2 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) n 1 1 0 0 0 0 0 -- -- 0 -- N 141 103 207 103 51 25 12 -- -- 1 -- 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -- -- 0.00 -- n 1 1 0 0 0 0 0 0 -- -- -- N 148 108 217 108 54 26 13 6 -- -- -- -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 -- -- -- 2.097152 Error (%)
RENESAS 355
Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode (cont)
(MHz) 2.4576 Bit Rate(bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 -- 0 N 174 127 255 127 63 31 15 7 3 -- 1 Error (%) n -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- 3 Error (%) n 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -- 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 3.6864 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00
Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode (cont)
(MHz) 4 Bit Rate(bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- Error (%) n 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 -- 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 4.9152 Error (%) n 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73
RENESAS 356
Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode (cont)
(MHz) 6 Bit Rate(bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) n -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 9 5 4 6.144 Error (%) n 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 2 2 1 1 0 0 0 0 0 -- 0 N 130 95 191 95 191 95 47 23 11 -- 5 7.3728 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00
Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode (cont)
(MHz) 8 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 -- N 141 103 207 103 207 103 51 25 12 7 -- Error (%) n 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -- 2 2 1 1 0 0 0 0 0 0 0 9.8304 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) n -0.26 2 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2 2 1 1 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34
-1.70 0 0.00 0
RENESAS 357
Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode (cont)
(MHz) 12.288 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) n 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 2 2 2 1 1 0 0 0 0 0 -- 14 N 248 181 90 181 90 181 90 45 22 13 -- Error (%) n -0.17 3 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16
-0.93 0 -0.93 0 0.00 -- 0 0
Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode (cont)
(MHz) 17.2032 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 27 16 13 Error (%) n 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 3 2 2 1 1 0 0 0 0 0 0 18 N 79 233 116 233 116 233 116 58 28 17 14 Error (%) n -0.12 3 0.16 0.16 0.16 0.16 0.16 0.16 2 1 1 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73
-0.69 0 1.02 0.00 0 0
-2.34 0
RENESAS 358
Table 13.4 Bit Rates and BRR Settings in Clocked Synchronous Mode
(MHz) Bit Rate (bits/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M Note Settings with an error of 1% or less are recommended. Blank: No setting available --: Setting possible, but error occurs : Continuous transmit/receive not possible The BRR setting is calculated as follows: Asynchronous mode N = [/(64 x 2 2n - 1 x B)] x 10 6 - 1 Clocked synchronous mode N = [/(8 x 2 2n - 1 x B)] x 10 6 - 1 B: bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) : frequency (MHz) n: baud rate generator clock source (n = 0, 1, 2, 3) For the clock sources and values of n, see table 13.5. 2 n 3 2 1 1 0 0 0 0 0 0 0 0 N 70 124 249 124 199 99 49 19 9 4 1 0 n -- 2 2 1 1 0 0 0 0 0 0 0 0 4 N -- 249 124 249 99 199 99 39 19 9 3 1 0* n -- 3 2 2 1 1 0 0 0 0 0 0 0 -- 8 N -- 124 249 124 199 99 199 79 39 19 7 3 1 -- n -- -- -- -- 1 1 0 0 0 0 0 0 -- 0 10 N -- -- -- -- 249 124 249 99 49 24 9 4 -- 0* n -- 3 3 2 2 1 1 0 0 0 0 0 0 -- -- 16 N -- 249 124 249 99 199 99 159 79 39 15 7 3 -- -- n -- -- -- -- 2 1 1 0 0 0 0 0 0 0 0 20 N -- -- -- -- 124 249 124 199 99 49 19 9 4 1 0*
RENESAS 359
SMR Settings n 0 1 2 3 Clock Source /4 /16 /24 CKS1 0 0 1 1 CKS0 0 1 0 1
Find the bit rate error for the asynchronous mode by the following formula. Error (%) = {( x 10 6)/[(N + 1) x B x 64 x 22n - 1 ] - 1 } x 100
RENESAS 360
Table 13.5 indicates the maximum bit rates in the asynchronous mode when the baud rate generator is being used. Tables 13.6 and 13.7 show the maximum rates for external clock input. Table 13.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode)
Settings (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 Maximum Bit Rate (bits/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 614400 625000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RENESAS 361
Table 13.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode)
(MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6834 4.0000 4.3008 4.5000 4.9152 5.0000 Maximum Bit Rate (bits/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 153600 156250 187500 192000 218750 230400 250000 268800 281250 307200 312500
RENESAS 362
Table 13.7 Maximum Bit Rates during External Clock Input (Clocked Synchronous Mode)
(MHz) 2 4 6 8 10 12 14 16 18 20 External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 Maximum Bit Rate (bits/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3
13.3
13.3.1
Operation
Overview
The SCI has an asynchronous mode in which characters are synchronized individually, and a clocked synchronous mode in which communication is synchronized with clock pulses. Serial communication is possible in either mode. Asynchronous/clocked synchronous mode and the communication format are selected in the serial mode register (SMR), as shown in table 13.8. The SCI clock source is selected by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR), as shown in table 13.9. Asynchronous Mode: * * * * Data length is selectable: seven or eight bits. Parity and multiprocessor bits are selectable. So is the stop bit length (one or two bits). The preceding selections constitute the communication format and character length. In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors (ORER), and the break state. An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.)
RENESAS 363
Clocked Synchronous Mode: * * * The communication format has a fixed eight-bit data length. In receiving, it is possible to detect overrun errors (ORER). An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices. When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used.
Table 13.8 Serial Mode Register Settings and SCI Communication Formats
SMR Settings Mode Asynchronous Bit 7: Bit 6: Bit 5: Bit 2: Bit 3: C/A CHR PE MP STOP 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Asynchronous (multiprocessor format) 0 * * 1 * * Clocked synchronous 1 * * * 1 0 1 0 1 * 8-bit Absent 7-bit 8-bit Absent Present Present 7-bit Absent Present SCI Communication Format Data Parity Length Bit 8-bit Absent MultiproStop Bit cessor Bit Length Absent 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None
Note: Asterisks (*) in the table indicate don't-care bits.
RENESAS 364
Table 13.9
SMR and SCR Settings and SCI Clock Source Selection
SMR SCR Settings Bit 1: CKE1 0 Bit 0: CKE0 0 1 1 0 1 External SCI Transmit/Receive Clock Clock Source SCK Pin Function* Internal SCI does not use the SCK pin Outputs a clock with frequency matching the bit rate Inputs a clock with frequency 16 times the bit rate
Mode
Bit 7: C/A
Asynchronous 0 mode
Clocked synchronous mode
1
0
0 1
Internal
Outputs the serial clock
1
0 1
External
Inputs the serial clock
Note: Select the function in combination with the pin function controller (PFC).
RENESAS 365
13.3.2
Operation in Asynchronous Mode
In the asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 13.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in the asynchronous mode, the SCI synchronizes on the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit.
1 Serial data 0 Start bit
(LSB) D0 D1 D2 D3 D4 D5 D6
(MSB) D7
Idling (mark state) 1 0/1 Parity bit 1 1 Stop bit
Transmit/receive data 1 bit 7 or 8 bits 1 or no bit 1 or 2 bits
One unit of communication (characters or frames)
Figure 13.2 Data Format in Asynchronous Communication (Example: 8-bit data with parity and two stop bits)
RENESAS 366
Transmit/Receive Formats: Table 13.10 shows the 12 communication formats that can be selected in the asynchronous mode. The format is selected by settings in the serial mode register (SMR). Table 13.10
SMR Bits CHR PE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 START START START START START START START START START START START START 2 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP MPB MPB MPB MPB STOP STOP STOP STOP STOP STOP STOP STOP STOP 11 12
Serial Communication Formats (asynchronous mode)
8-Bit data 8-Bit data 8-Bit data 8-Bit data 7-Bit data 7-Bit data 7-Bit data 7-Bit data 8-Bit data 8-Bit data 7-Bit data 7-Bit data
--: Don't care bits. Note: START: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR) (table 13.9). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the
RENESAS 367
desired bit rate. When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 13.3 so that the rising edge of the clock occurs at the center of each transmit data bit.
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 13.3 Phase Relationship Between Output Clock and Serial Data (asynchronous mode) Transmitting and Receiving Data (SCI initialization (asynchronous mode)): Before transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. Figure 13.4 is a sample flowchart for initializing the SCI. The procedure for initializing the SCI is as follows: 1. Select the communication format in the serial mode register (SMR). 2. Write the value corresponding to the bit rate in the bit rate register (BRR) unless an external clock is used. 3. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE and RE cleared to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made to SCR. 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1. Also set RIE, TIE, TEIE and MPIE as necessary. Setting TE or RE enables the SCI to use the TxD or RxD pin. The initial states are the mark transmit state, and the idle receive state (waiting for a start bit).
RENESAS 368
Start of initialization Clear TE and RE bits to 0 in SCR Select communication format in SMR (1) Set value in BRR Set CKE1 and CKE0 bits in SCR (leaving TE and RE cleared to 0) Wait No (2)
(3)
1-bit interval elapsed? Yes Set TE or RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE as necessary
(4)
End
Note:
Circled numbers refer to the preceding procedure.
Figure 13.4 Sample Flowchart for SCI Initialization Transmitting Serial Data (asynchronous mode): Figure 13.5 shows a sample flowchart for transmitting serial data. The procedure for transmitting serial data is as follows: 1. SCI initialization: select the TxD pin function with the PFC. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. 3. To continue transmitting serial data: read the TDRE bit to check whether it is safe to write (1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-dataempty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. 4. To output a break signal at the end of serial transmission: set the DR bit to 0 (I/O data port register), then clear TE to 0 in SCR and set the TxD pin function as output port with the PFC.
RENESAS 369
Initialize Start transmitting Read TDRE bit in SSR
(1)
(2) No
TDRE = 1? Yes Write transmit data in TDR and clear TDRE bit to 0 in SSR (3) All data transmitted? Yes Read TEND bit in SSR
No
TEND = 1? Yes Output break signal? (4) Yes Set DR = 0 Clear TE bit of SCR to 0; Select theTxD pin function as an output port with the PFC Transmission ends
No
No
Note:
Circled numbers refer to the preceding procedure.
Figure 13.5 Sample Flowchart for Transmitting Serial Data
RENESAS 370
In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from the TDR into the transmit shift register (TSR). 2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in the SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: 1. Start bit: one 0 bit is output. 2. Transmit data: seven or eight bits of data are output, LSB first. 3. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. 4. Stop bit: one or two 1 bits (stop bits) are output. 5. Mark state: output of 1 bits continues until the start bit of the next transmit data. 6. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new data from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in the SSR, outputs the stop bit, then continues output of 1 bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in the SCR is set to 1, a transmit-end interrupt (TEI) is requested. Figure 13.6 shows an example of SCI transmit operation in the asynchronous mode.
RENESAS 371
1 Serial data
Start bit 0 D0 D1
Data D7
Parity Stop Start bit bit bit 0/1 1 0 D0 D1
Data
Parity Stop 1 bit bit Idle (mark D7 0/1 1 state)
TDRE
TEND TXI TXI interrupt request handler writes data in TDR and clears TDRE to 0 1 frame TXI request
TEI request
Figure 13.6 Example of SCI Transmit Operation in Asynchronous Mode (8-bit data with parity and one stop bit) Receiving Serial Data (asynchronous mode): Figure 13.7 shows a sample flowchart for receiving serial data. The procedure for receiving serial data is listed below. 1. SCI initialization: select the RxD pin function with the PFC. 2. Receive error handling and break detection: if a receive error occurs, read the ORER, PER and FER bits of the SSR to identify the error. After executing the necessary error handling, clear ORER, PER and FER all to 0. Receiving cannot resume if ORER, PER or FER remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 3. SCI status check and receive data read: read the serial status register (SR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. To continue receiving serial data: read RDRF and RDR, and clear RDRF to 0 before the stop bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary.
RENESAS 372
Initialization
(1)
Start receiving
Read the ORER, PER, and FER bits of the SSR Yes (2) Error handling (3)
PER, FER, ORER = 1? No Read the RDRF bit of the SSR No
RDRF = 1? Yes
Read the RDR's receive data (4) and clear the SSR's RDRF bit to 0
No
Total count received? Yes Clear the RE bit of the SCR to 0
Reception ends
Note:
Circled numbers refer to the preceding procedure.
Figure 13.7 Sample Flowchart for Receiving Serial Data
RENESAS 373
Start of error handling
No
ORER = 1? Yes Overrun error handling
No
FER = 1? Yes Break? No Framing error handling Clear RE bit to 0 in SCR Yes
No
PER = 1? Yes Parity error handling
Clear ORER, PER, and FER to 0 in SSR
End
Note:
Circled numbers refer to the preceding procedure.
Figure 13.7 Sample Flowchart for Receiving Serial Data (cont)
RENESAS 374
In receiving, the SCI operates as follows: 1. The SCI monitors the receive data line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into the RSR in order from the LSB to the MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check: The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in the SMR. b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. c. Status check: RDRF must be 0 so that receive data can be loaded from the RSR into the RDR. If these checks all pass, the SCI sets RDRF to 1 and stores the received data in the RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 13.11. Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1. Be sure to clear the error flags.
4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the SCR, the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER, PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Figure 13.8 shows an example of SCI receive operation in the asynchronous mode. Table 13.11 Receive Error Conditions and SCI Operation
Receive Error Overrun error Framing error Parity error Abbreviation ORER FER PER Condition Receiving of next data ends while RDRF is still set to 1 in SSR Stop bit is 0 Parity of receive data differs from even/odd parity setting in SMR Data Transfer Receive data not loaded from RSR into RDR Receive data loaded from RSR into RDR Receive data loaded from RSR into RDR
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1 Serial data
Start bit 0 D0 D1
Data D7
Parity Stop Start bit bit bit 0/1 1 0 D0 D1
Data D7
Parity Stop bit bit 0/1 0
1 Idle (mark state)
TDRE
FER
RXI request
1 frame
RXI interrupt handler reads data in RDR and clears RDRF to 0
Framing error, ERI request
Figure 13.8 Example of SCI Receive Operation (8-bit data with parity and one stop bit) 13.3.3 Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in the asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. The receiving processor with a matching ID continues to receive further incoming data. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 13.9 shows the example of communication among processors using the multiprocessor format.
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Transmitting processor Serial communication line
Receiving processor A (ID = 01)
Receiving processor B (ID = 02)
Receiving processor C (ID = 03)
Receiving processor D (ID = 04)
Serial data
H'01 (MPB = 1) ID-sending cycle: receiving processor address MPB: multiprocessor bit
H'AA (MPB = 0) Data-sending cycle: data sent to receiving processor specified by ID
Figure 13.9 Example of Communication among Processors Using Multiprocessor Format (sending data H'AA to receiving processor A) Communication Formats: Four formats are available. Parity-bit settings are ignored when the multiprocessor format is selected. For details see table 13.8. Clock: See the description in the asynchronous mode section. Transmitting Multiprocessor Serial Data: Figure 13.10 shows a sample flowchart for transmitting multiprocessor serial data. The procedure for transmitting multiprocessor serial data is listed below. 1. SCI initialization: select the TxD pin function with the PFC. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT (multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0. 3. To continue transmitting serial data: read the TDRE bit to check whether it is safe to write (1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-dataempty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. 4. To output a break signal at the end of serial transmission: set the DR bit to 0 (I/O data port register), then clear TE to 0 in SCR and set the TxD pin function as output port with the PFC.
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Initialize Start transmitting Read TDRE bit in SSR
(1)
(2) No
TDRE = 1? Yes Write transmit data in TDR and set MPBT in SSR Clear TDRE bit to 0
All data transmitted? Yes Read TEND bit in SSR
No
(3)
TEND = 1? Yes Output break signal? Yes Set DR = 0 Clear TE bit to 0 in SCR; select theTxD pin function as an output port with the PFC End
No
No (4)
Note:
Circled numbers refer to the preceding procedure.
Figure 13.10 Sample Flowchart for Transmitting Multiprocessor Serial Data In transmitting serial data, the SCI operates as follows:
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1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from the TDR into the transmit shift register (TSR). 2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin (figure 13.11): 1. 2. 3. 4. 5. 6. Start bit: one 0 bit is output. Transmit data: seven or eight bits are output, LSB first. Multiprocessor bit: one multiprocessor bit (MPBT value) is output. Stop bit: one or two 1 bits (stop bits) are output. Mark state: output of 1 bits continues until the start bit of the next transmit data. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in the SSR to 1, outputs the stop bit, then continues output of 1 bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in the SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
Multiprocessor Stop Start bit bit bit D7 0/1 1 0 D0 Multiprocessor Stop 1 Data bit bit Idle (mark D1 D7 0/1 1 state)
1 Serial data
Start bit 0 D0 D1
Data
TDRE
TEND
TXI TXI interrupt request handler writes data in TDR and clears TDRE to 0 1 frame
TXI request
TEI request
Figure 13.11 Example of SCI Multiprocessor Transmit Operation (8-bit data with multiprocessor bit and one stop bit)
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Receiving Multiprocessor Serial Data: Figure 13.12 shows a sample flowchart for receiving multiprocessor serial data. The procedure for receiving multiprocessor serial data is listed below. 1. SCI initialization: select the RxD pin function with the PFC. 2. ID receive cycle: set the MPIE bit in the serial control register (SCR) to 1. 3. SCI status check and compare to ID reception: read the serial status register (SSR), check that RDRF is set to 1, then read data from the receive data register (RDR) and compare with the processor's own ID. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. 4. Receive error handling and break detection: if a receive error occurs, read the ORER and FER bits in SSR to identify the error. After executing the necessary error handling, clear both ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 5. SCI status check and data receiving: read SSR, check that RDRF is set to 1, then read data from the receive data register (RDR).
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Initialization Start receiving Set the MPIE bit of the SCR to 1 Read the ORER and FER bits of the SSR FER = 1? or ORER = 1? No Read the RDRF bit of the SSR No
(1)
(2)
Yes
(3)
RDRF = 1? Yes Read the receive data of the RDR
No
Own ID? Yes Read the ORER and FER bits of the SSR FER = 1? or ORER = 1? No Read the SSR's RDRF bit RDRF = 1? Yes Read the RDR's receive data (5) No Yes
No
Total count received? Yes Clear the RE bit of the SCR to 0 Reception ends
(4) Error handling
Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data
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Start of error handling
No
ORER = 1? Yes Overrun error handling
No
FER = 1? Yes Break? No Framing error handling Clear RE bit to 0 in SCR Yes
Clear ORER and FER to 0 in SSR
End
Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (cont)
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Figure 13.13 shows an example of SCI receive operation using a multiprocessor format.
1 Serial data
Start bit 0 D0
Stop Start Data ID1 MPB bit bit D1 D7 1 1 0 D0
Data 1 D1 D7
Stop 1 MPB bit 0 1 Idle (mark state)
MPB
MPIE
RDRF
RDR value RXI request, (multiprocessor interrupt) MPIE = 0 RXI interrupt handler reads data in RDR and clears RDRF to 0
ID1
Not own ID, so MPIE is set to 1 again
No RXI interrupt, RDR maintains state
Figure 13.13 Example of SCI Receive Operation (own ID does not match data) (8-bit data with multiprocessor bit and one stop bit)
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1 Serial data
Start bit 0 D0
Stop Start Data ID1 MPB bit bit D1 D7 1 1 0 D0
Data 1 D1 D7
Stop 1 MPB bit 0 1 Idle (mark state)
MPB
MPIE
RDRF
RDR value RXI request, (multiprocessor interrupt) MPIE = 0 RXI interrupt handler reads data in RDR and clears RDRF to 0
ID1
Not own ID, so MPIE is set to 1 again
No RXI interrupt, RDR maintains state
Figure 13.13 Example of SCI Receive Operation (own ID matches data) (8-bit data with multiprocessor bit and one stop bit) (cont) 13.3.4 Clocked Synchronous Operation
In the clocked synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 13.14 shows the general format in clocked synchronous serial communication.
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Transfer direction One unit (character or frame) of serial data * Serial clock LSB Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 *
Note:
High except in continuous transmitting or receiving.
Figure 13.14 Data Format in Clocked Synchronous Communication In clocked synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data are guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In the clocked synchronous mode, the SCI transmits or receives data by synchronizing with the falling edge of the serial clock. Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR). See table 13.6. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. Figure 13.15 shows an example of SCI transmit operation. In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from the TDR into the transmit shift register (TSR). 2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock source
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is selected, the SCI outputs data in synchronization with the input clock. Data are output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data from the TDR into the TSR, transmits the MSB, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in the SSR to 1, transmits the MSB, then holds the transmit data pin (TxD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in the SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. 4. After the end of serial transmission, the SCK pin is held in the high state.
Transmit direction Serial clock
LSB
Serial data Bit 0 Bit 1
MSB
Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TDRE
TEND
TXI request
TXI interrupt handler writes data in TDR and clears TDRE to 0 1 frame
TXI request
TEI request
Figure 13.15 Example of SCI Transmit Operation Transmitting and Receiving Data: SCI Initialization (clocked synchronous mode): Before transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. Figure 13.16 is a sample flowchart for initializing the SCI. The procedure for initializing the SCI is listed below.
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1. Select the communication format in the serial mode register (SMR). 2. Write the value corresponding to the bit rate in the bit rate register (BRR) unless an external clock is used. 3. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE and RE cleared to 0. 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1. Also set RIE, TIE, TEIE and MPIE. Setting the corresponding bit of the pin function controller, TE and RE enables the SCI to use the TxD or RxD pin.
Start of initialization Clear TE and RE bits to 0 in SCR Select communication format in SMR (1) Set value in BRR Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCR (leaving TE and RE cleared to 0) Wait 1-bit interval elapsed? Yes Set TE or RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE (4) No
(2)
(3)
End
Note:
High except in continuous transmitting or receiving.
Figure 13.16 Sample Flowchart for SCI Initialization
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Transmitting Serial Data (clocked synchronous mode): Figure 13.17 shows a sample flowchart for transmitting serial data. The procedure for transmitting serial data is listed below. 1. SCI initialization: select the TxD pin function with the PFC. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 3. To continue transmitting serial data: read the TDRE bit to check whether it is safe to write (1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-dataempty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically.
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Initialize Start transmitting
(1)
Read TDRE bit in SSR No
(2)
TDRE = 1? Yes Write transmit data in TDR and clear TDRE bit to 0 in SSR
All data transmitted? Yes Read TEND bit in SSR
No
(3)
TEND = 1? Yes Clear TE bit SCR to 0 Transmission ends
No
Figure 13.17 Sample Flowchart for Serial Transmitting Receiving Serial Data (clocked synchronous mode): Figure 13.18 shows a sample flowchart for receiving serial data. When switching from the asynchronous mode to the clocked synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled. Figure 13.19 shows an example of SCI recieve operation. The procedure for recieving serial data is listed below. 1. SCI initialization: select the RxD pin function with the PFC. 2. Receive error handling: if a receive error occurs, read the ORER bit in SSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving
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cannot resume if ORER remains set to 1. 3. SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. To continue receiving serial data: read RDR, and clear RDRF to 0 before the frame MSB (bit 7) of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary.
Initialization Start receiving Read the ORER bit of the SSR
(1)
ORER = 1? No Read RDRF bit of the SSR No
Yes (2) Error handling (3)
RDRF = 1? Yes
Read the RDR's receive data (4) and clear the SSR's RDRF bit to 0 No
Total count received? Yes Clear the RE bit of the SCR to 0 Reception ends
Figure 13.18 Sample Flowchart for Serial Receiving
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Error handling No
ORER = 1? Yes Overrun error handling
Clear ORER bit of SSR to 0 End
Figure 13.18 Sample Flowchart for Serial Receiving (cont)
Receive direction Serial clock
Serial data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI request
RXI interrupt handler reads data in RDR and clears RDRF to 0 1 frame
RXI request
Overrun error, ERI request
Figure 13.19 Example of SCI Receive Operation In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into the RSR in order from the LSB to the MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from the RSR into the
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RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in the RDR. If the check does not pass (receive error), the SCI operates as indicated in table 13.8. When the error flag is set to 1 and the RDRF bit is cleared to 0, the RDRF bit will not be set to 1 during reception. When restarting the reception, make sure to clear the error flag to 0. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the SCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Transmitting and Receiving Serial Data Simultaneously (clocked synchronous mode): Figure 13.20 shows a sample flowchart for transmitting and receiving serial data simultaneously. The procedure for transmitting and receiving serial data simultaneously is listed below. 1. SCI initialization: select the TxD and RxD pin function with the PFC. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1. 3. Receive error handling: if a receive error occurs, read the ORER bit in SSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 4. SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 5. To continue transmitting and receiving serial data: read the RDRF bit and RDR, and clear RDRF to 0 before the frame MSB (bit 7) of the current frame is received. Also read the TDRE bit to check whether it is safe to write (1); if so, write data in TDR, then clear TDRE to 0 before the MSB (bit 7) of the current frame is transmitted. When the DMAC is started by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. When the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically.
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Initialization Start transmitting and receiving
(1)
Read TDRE bit of the SSR No
(2)
TDRE = 1? Yes Write transmit data to the TDR and clear the TDRE bit of the SSR to 0 Read the ORER bit of the SSR Yes (3) Error handling
ORER = 1? No
Read the SSR's RDRF bit No
(4)
RDRF = 1? Yes Read the receive data of the RDR and clear the RDRF bit of the SSR to 0 (5)
No
Total count transmitted and received? Yes Clear the TE and RE bits of the SCR to 0 Transmitting/receiving ends
Note:
In switching from transmitting or receiving to simultaneous transmitting and receiving, clear both TE and RE to 0, then set both TE and RE to 1.
Figure 13.20 Sample Flowchart for Serial Transmitting
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13.4
SCI Interrupt Sources and the DMAC
The SCI has four interrupt sources in each channel: transmit-end (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI). Table 13.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCR). Each interrupt request is sent separately to the interrupt controller. TXI is requested when the TDRE bit in the SSR is set to 1. TXI can start the direct memory access controller (DMAC) to transfer data. TDRE is automatically cleared to 0 when the DMAC executes the data transfer to the transmit data register (TDR). RXI is requested when the RDRF bit in the SSR is set to 1. RXI can start the DMAC to transfer data. RDRF is automatically cleared to 0 when the DMAC executes the data transfer to the receive data register (RDR). ERI is requested when the ORER, PER, or FER bit in the SSR is set to 1. ERI cannot start the DMAC. TEI is requested when the TEND bit in the SSR is set to 1. TEI cannot start the DMAC. A TXI interrupt indicates that transmit data writing is enabled. A TEI interrupt indicates that the transmit operation is complete. Table 13.12
Interrupt Source ERI RXI TXI TEND
SCI Interrupt Sources
Description Receive error (ORER, PER, or FER) Receive data full (RDRF) Transmit data empty (TDRE) Transmit end (TEND) DMAC Availability No Yes Yes No Priority High Low
13.5
Usage Notes
Note the following points when using the SCI. TDR Write and TDRE Flags: The TDRE bit in the serial status register (SSR) is a status flag indicating loading of transmit data from the TDR into the TSR. The SCI sets TDRE to 1 when it transfers data from the TDR to the TSR. If new data is written in the TDR when TDRE is 0, the old data stored in the TDR will be lost because these data have not yet been transferred to the TSR. Before writing transmit data to the TDR, be sure to check that TDRE is set to 1. Simultaneous Multiple Receive Errors: Table 13.13 indicates the state of the SSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs, the RSR contents cannot be transferred to the RDR, so receive data is lost.
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Table 13.13 SSR Status Flags and Transfer of Receive Data
SSR Status Flags Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error O: X: RDRF 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Transfer RSR RDR X O O X X O X
Receive data is transferred from RSR-RDR. Receive data is not transferred from RSR-RDR.
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again. Sending a Break Signal: When TE is cleared to 0 the TxD pin becomes an I/O port, the level and direction (input or output) of which are determined by the data register (DR) of the I/O port and the control register (CR) of the PFC. This feature can be used to send a break signal. The DR value substitutes for the mark state until the PFC setting is performed. The DR bits should therefore be set as an output port that outputs 1 beforehand. To send a break signal during serial transmission, clear the DR bit to 0, and select output port as the TxD pin function by the PFC. When TE is cleared to 0, the transmitter is initialized, regardless of its current state. Receive Error Flags and Transmitter Operation (clocked synchronous mode only): When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that clearing RE to 0 does not clear the receive error flags. Receive Data Sampling Timing and Receive Margin in the Asynchronous Mode: In the asynchronous mode, the SCI operates on a base clock of 16 times the bit rate frequency. In receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse. See figure 13.21.
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16 clocks 8 clocks Internal base clock Receive data (RxD) Synchronization sampling timing Data sampling timing
0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5
-7.5 clocks Start bit
+7.5 clocks D0 D1
Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in the asynchronous mode can therefore be expressed as in equation 1. Equation 1:
M= M: N: D: L: F: 0.5 - 1 2N - (L - 0.5)F - D
- 0.5
N
(1 + F ) x 100%
Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0-1.0) Frame length (L = 9-12) Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation 2. Equation 2:
D M = 0.5, F = 0 = (0.5 - 1/(2 x 16)) x 100% = 46.875% (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20-30%. Constraints on DMAC Use:
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*
*
When using an external clock source for the serial clock, update the TDR with the DMAC, and then after five system clocks or more elapse, input a transmit clock. If a transmit clock is input in the first four system clocks after the TDR is written, an error may occur (figure 13.22). Before reading the receive data register (RDR) with the DMAC, select the receive-data-full interrupt of the SCI as a start-up source using the resource select bit (RS) in the channel control register (CHCR).
SCK t TDRE
D0
D1
D2
D3
D4
D5
D6
D7
Note:
During external clock operation, an error may occur if t is 4 or less.
Figure 13.22 Clocked Synchronous Transmitting Example with DMAC Cautions for Clocked Synchronous External Clock Mode: * * * Set TE = RE = 1 only when the external clock SCI is 1. Do not set TE = RE = 1 until at least 4 clocks after the external clock SCK has changed from 0 to 1. When receiving, RDRF = 1 when RE is set to zero 2.5-3.5 clocks after the rise edge of the RxD D7 bit SCK input, but it cannot be copied to RDR.
Caution for Clocked Synchronous Internal Clock Mode: When receiving, RDRF = 1 when RE is set to zero 1.5 clocks after the rise edge of the RxD D7 bit SCK input, but it cannot be copied to RDR.
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Section 14 Pin Function Controller (PFC)
14.1 Overview
The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the direction of input/output. The pin function and input/output direction can be selected for each pin individually without regard to the operating mode of the LSI. Table 14.1 lists the multiplexed pins. Table 14.1 List of Multiplexed Pins
Port A A A A A A A A A A A Function 1 Function 2 (related module) (related module) PA15 I/O (port) PA14 I/O (port) PA13 I/O (port) PA12 I/O (port) PA11 I/O (port) PA10 I/O (port) PA9 I/O (port) PA8 I/O (port) PA7 I/O (port) PA6 I/O (port) PA5 I/O (port) IRQ3 input (INTC) IRQ2 input (INTC) IRQ1 input (INTC) IRQ0 input (INTC) DPH I/O (D bus) DPL I/O (D bus) AH output (BSC) BREQ input (system) BACK output (system) RD output (BSC) WRH output (BSC) (LBS output (BSC))* 1 Function 3 (related module) DREQ1 input (DMAC) DACK1 output (DMAC) Function 4 (related module) -- -- Pin # 68 67 66
TCLKB input (ITU) DREQ0 input (DMAC)
TCLKA input (ITU) DACK0 output (DMAC) 65 TIOCB1 I/O (ITU) TIOCA1 I/O (ITU) -- -- -- -- -- -- -- 64 62
IRQOUT output (INTC) 61 -- -- -- -- 60 58 57 56
A
PA4 I/O (port)
WRL output -- (BSC) (WR output (BSC))*1 CS7 output (BSC) CS6 output (BSC) CS5 output (BSC) CS4 output (BSC) WAIT input (BSC) TIOCB0 I/O (ITU) RAS output (BSC) TIOCA0 I/O (ITU)
--
55
A A A A
PA3 I/O (port) PA2 I/O (port) PA1 I/O (port) PA0 I/O (port)
-- -- -- --
54 53 52 51
RENESAS 399
Table 14.1 List of Multiplexed Pins (cont)
Port B B B B B B B B B B B B B B B B -- -- Function 1 Function 2 (related module) (related module) PB15 I/O (port) PB14 I/O (port) PB13 I/O (port) PB12 I/O (port) PB11 I/O (port) PB10 I/O (port) PB9 I/O (port) PB8 I/O (port) PB7 I/O (port) PB6 I/O (port) PB5 I/O (port) PB4 I/O (port) PB3 I/O (port) PB2 I/O (port) PB1 I/O (port) PB0 I/O (port) IRQ7 input (INTC) IRQ6 input (INTC) IRQ5 input (INTC) IRQ4 input (INTC) TxD1 output (SCI) RxD1 input (SCI) TxD0 output (SCI) RxD0 input (SCI) Function 3 (related module) -- -- SCK1 I/O (SCI) SCK0 I/O (SCI) TP11 output (TPC) TP10 output (TPC) TP9 output (TPC) TP8 output (TPC) Function 4 (related module) TP15 output (TPC) TP14 output (TPC) TP13 output (TPC) TP12 output (TPC) -- -- -- -- Pin # 100 99 98 97 96 95 94 93 91 90 89 87 86 85 84 83 47 49
TCLKD input (ITU) TOCXB4 output (ITU) TP7 output (TPC) TCLKC input (ITU) TOCXA4 output (ITU) TP6 output (TPC) TIOCB4 I/O (ITU) TIOCA4 I/O (ITU) TIOCB3 I/O (ITU) TIOCA3 I/O (ITU) TIOCB2 I/O (ITU) TIOCA2 I/O (ITU) TP5 output (TPC) TP4 output (TPC) TP3 output (TPC) TP2 output (TPC) TP1 output (TPC) TP0 output (TPC) -- -- -- -- -- -- -- -- -- --
CS1 output (BSC) CASH output (BSC) CS3 output (BSC) CASL output (BSC)
INTC: Interrupt controller DMAC: Direct memory access controller ITU: 16-bit integrated timer pulse unit D bus: Data bus control BSC: Bus state controller System: System control SCI: Serial communications interface TPC: Programmable timing pattern controller Port: I/O port Notes: 1. The bus control register of the bus state controller handles switching between the two functions.
RENESAS 400
14.2
Register Configuration
Table 14.2 summarizes the registers of the pin function controller. Table 14.2 Pin Function Controller Registers
Name Port A I/O register Port A control register 1 Port A control register 2 Port B I/O register Port B control register 1 Port B control register 2 Column address strobe pin control register Abbreviation R/W PAIOR PACR1 PACR2 PBIOR PBCR1 PBCR2 CASCR R/W R/W R/W R/W R/W R/W R/W Initial Value H'0000 H'3302 H'FF95 H'0000 H'0000 H'0000 H'5FFF Address H'5FFFFC4 H'5FFFFC8 H'5FFFFCA H'5FFFFC6 H'5FFFFCC H'5FFFFCE H'5FFFFEE Access Size 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32
14.3
14.3.1
Register Descriptions
Port A I/O Register (PAIOR)
The port A I/O register (PAIOR) is a 16-bit read/write register that selects input or output for individual pins on a bit-by-bit basis. Bits PA15IOR-PA0IOR correspond to pins PA15/IRQ3/DREQ1-PA0/CS4/TIOCA0. PAIOR is enabled when the port A pins function as input/outputs (PA15-PA0) and for ITU input capture and output compare (TIOCA1, TIOCA0, TIOCB1, and TIOCB0). For other functions, they are disabled. For port A pin functions PA15- PA0 and TIOCA1, TIOCA0, TIOCB1, and TIOCB0, a given pin in port A is an output pin if its corresponding PAIOR bit is set to 1, and an input pin if the bit is cleared to 0. PAIOR is initialized to H'0000 by power-on resets; however, it is not initialized for manual resets, standby mode, or sleep mode.
RENESAS 401
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W:
15 PA15 IOR 0 R/W 7 PA7 IOR 0 R/W
14 PA14 IOR 0 R/W 6 PA6 IOR 0 R/W
13 PA13 IOR 0 R/W 5 PA5 IOR 0 R/W
12 PA12 IOR 0 R/W 4 PA4 IOR 0 R/W
11 PA11 IOR 0 R/W 3 PA3 IOR 0 R/W
10 PA10 IOR 0 R/W 2 PA2 IOR 0 R/W
9 PA9 IOR 0 R/W 1 PA1 IOR 0 R/W
8 PA8 IOR 0 R/W 0 PA0 IOR 0 R/W
14.3.2
Port A Control Registers (PACR1 and PACR2)
PACR1 and PACR2 are 16-bit read/write registers that select the functions of the sixteen multiplexed pins of port A. PACR1 selects the function of the top eight bits of port A; PACR2 selects the function of the bottom eight bits of port A. PACR1 and PACR2 are initialized to H'3302 and H'FF95 respectively by power-on resets but are not initialized for manual resets, standby mode, or sleep mode. PACR1:
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 PA15 MD1 0 R/W 7 PA11 MD1 0 R/W 14 PA15 MD0 0 R/W 6 PA11 MD0 0 R/W 13 PA14 MD1 1 R/W 5 PA10 MD1 0 R/W 12 PA14 MD0 1 R/W 4 PA10 MD0 0 R/W 11 PA13 MD1 0 R/W 3 10 PA13 MD0 0 R/W 2 9 PA12 MD1 1 R/W 1 -- 1 -- 8 PA12 MD0 1 R/W 0 PA8MD 0 R/W
PA9MD1 PA9MD0 0 R/W 0 R/W
*
Bits 15 and 14 (PA15 mode (PA15MD1 and PA15MD0)): PA15MD1 and PA15MD0 select the function of the PA15/IRQ3/DREQ1 pin.
RENESAS 402
Bit 15: PA15MD1 0
Bit 14: PA15MD0 0 1
Function Input/output (PA15) (initial value) Interrupt request input (IRQ3) Reserved DMA transfer request input (DREQ1)
1
0 1
*
Bits 13 and 12 (PA14 mode (PA14MD1 and PA14MD0)): PA14MD1 and PA14MD0 select the function of the PA14/IRQ2/DACK1 pin.
Bit 12: PA14MD0 0 1 Function Input/output (PA14) Interrupt request input (IRQ2) Reserved DMA transfer acknowledge output (DACK1) (initial value)
Bit 13: PA14MD1 0
1
0 1
*
Bits 11 and 10 (PA13 Mode (PA13MD1 and PA13MD0)): PA13MD1 and PA13MD0 select the function of the PA13/IRQ1/DREQ0/TCLKB pin.
Bit 10: PA13MD0 0 1 Function Input/output (PA13) (initial value) Interrupt request input (IRQ1) ITU timer clock input (TCLKB) DMA transfer request input (DREQ0)
Bit 11: PA13MD1 0
1
0 1
*
Bits 9 and 8 (PA12 mode (PA12MD1 and PA12MD0)): These bits select the function of the PA12/IRQ0/DACK0/TCLKA pin.
Bit 8: PA12MD0 0 1 Function Input/output (PA12) Interrupt request input (IRQ0) ITU timer clock input (TCLKA) DMA transfer acknowledge output (DACK0) (initial value)
Bit 9: PA12MD1 0
1
0 1
RENESAS 403
*
Bits 7 and 6 (PA11 mode (PA11MD1 and PA11MD0)): These bits select the function of the PA11/DPH/TIOCB1 pin.
Bit 6: PA11MD0 0 1 Function Input/output (PA11) (initial value) Upper data bus parity input/output (DPH) ITU input capture/output compare (TIOCB1) Reserved
Bit 7: PA11MD1 0
1
0 1
*
Bits 5 and 4 (PA10 mode (PA10MD1 and PA10MD0)): These bits select the function of the PA10/DPL/TIOCA1 pin.
Bit 4: PA10MD0 0 1 Function Input/output (PA10) (initial value) Lower data bus parity input/output (DPL) ITU input capture/output compare (TIOCA1) Reserved
Bit 5: PA10MD1 0
1
0 1
*
Bits 3 and 2 (PA9 mode (PA9MD1 and PA9MD0)): These bits select the function of the PA9/AH/IRQOUT pin.
Bit 2: PA9MD0 0 1 Function Input/output (PA9) (initial value) Address hold output (AH) Reserved Interrupt request output (IRQOUT)
Bit 3: PA9MD1 0
1
0 1
* *
Bit 1 (reserved): This bit always reads as 1. The write value should always be 1. Bit 0 (PA8 mode (PA8MD)): PA8MD selects the function of the PA8/BREQ.
Function Input/output (PA8) (initial value) Bus request input (BREQ)
Bit 0: PA8MD 0 1
RENESAS 404
PACR2:
Bit: Bit name: Initial value: R/W: Bit: 15 -- 1 -- 7 14 PA7MD 1 R/W 6 13 -- 1 -- 5 12 PA6MD 1 R/W 4 11 -- 1 -- 3 10 PA5MD 1 R/W 2 9 -- 1 -- 1 8 PA4MD 1 R/W 0
Bit name: PA3MD1 PA3MD0 PA2MD1 PA2MD0 PA1MD1 PA1MD0 PA0MD1 PA0MD0 Initial value: R/W: 1 R/W 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 1 R/W
* *
Bit 15 (reserved): This bit always reads as 1. The write value should always be 1. Bit 14 (PA7 mode (PA7MD)): PA7MD selects the function of the PA7/BACK pin.
Function Input/output (PA7) Bus request acknowledge output (BACK) (initial value)
Bit 14: PA7MD 0 1
* *
Bit 13 (reserved): This bit always reads as 1. The write value should always be 1. Bit 12 (PA6 mode (PA6MD)): PA6MD selects the function of the PA6/RD pin.
Function Input/output (PA6) Read output (RD) (initial value)
Bit 12: PA6MD 0 1
* *
Bit 11 (reserved): This bit always reads as 1. The write value should always be 1. Bit 10 (PA5 mode (PA5MD)): PA5MD selects the function of the PA5/WRH (LBS) pin.
Function Input/output (PA5) Upper write output (WRH) or lower byte strobe output (LBS) (initial value)
Bit 10: PA5MD 0 1
*
Bit 9 (reserved): This bit always reads as 1. The write value should always be 1.
RENESAS 405
*
Bit 8 (PA4 mode (PA4MD)): PA4MD selects the function of the PA4/WRL (WR) pin.
Function Input/output (PA4) Lower write output (WRL) or write output (WR) (initial value)
Bit 8: PA4MD 0 1
*
Bits 7 and 6 (PA3 mode (PA3MD1 and PA3MD0)): PA3MD1 and PA3MD0 select the function of the PA3/CS7/WAIT pin. This pin has a pull-up MOS that is used when it functions as a WAIT pin to allow selection of pull up or no pull up (for the WAIT pin) using the wait state control register of the bus state controller (BSC). There is no pull up when if functions as PA3 or CS7.
Bit 6: PA3MD0 0 1 Function Input/output (PA3) Chip select output (CS7) Wait state input (WAIT) (initial value) Reserved
Bit 7: PA3MD1 0
1
0 1
*
Bits 5 and 4 (PA2 mode (PA2MD1 and PA2MD0)): PA2MD1 and PA2MD0 select the function of the PA2/CS6/TIOCB0 pin.
Bit 4: PA2MD0 0 1 Function Input/output (PA2) Chip select output (CS6) (initial value) ITU input capture/output compare (TIOCB0) Reserved
Bit 5: PA2MD1 0
1
0 1
*
Bits 3 and 2 (PA1 mode (PA1MD1 and PA1MD0)): PA1MD1 and PA1MD0 select the function of the PA1/CS5/RAS pin.
Bit 2: PA1MD0 0 1 Function Input/output (PA1) Chip select output (CS5) (initial value) Row address strobe output (RAS) Reserved
Bit 3: PA1MD1 0
1
0 1
RENESAS 406
*
Bits 1 and 0 (PA0 mode (PA0MD1 and PA0MD0)): PA0MD1 and PA0MD0 select the function of the PA0/CS4/TIOCA0 pin.
Bit 0: PA0MD0 0 1 Function Input/output (PA0) Chip select output (CS4) (initial value) ITU input capture/output compare (TIOCA0) Reserved
Bit 1: PA0MD1 0
1
0 1
14.3.3
Port B I/O Register (PBIOR)
The port B I/O register (PBIOR) is a 16-bit read/write register that selects input or output for individual pins on a bit-by-bit basis. Bits PB15IOR-PB0IOR correspond to pins of port B. PBIOR is enabled when the port B pins function as input/outputs (PB15-PB0), for ITU input capture and output compare (TIOCA4, TIOCA3, TIOCA2, TIOCB4, TIOCB3, and TIOCB2), and as serial clocks (SCK1, SCK0). For other functions, they are disabled. For port B pin functions PB15-PB0, and TIOCA4, TIOCA3, TIOCA2, TIOCB4, TIOCB3, and TIOCB2, and SCK1/SCK0, a given pin in port B is an output pin if its corresponding PBIOR bit is set to 1, and an input pin if the bit is cleared to 0. PBIOR is initialized to H'0000 by power-on resets; however, it is not initialized for manual resets, standby mode, or sleep mode.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 PB15 IOR 0 R/W 7 PB7 IOR 0 R/W 14 PB14 IOR 0 R/W 6 PB6 IOR 0 R/W 13 PB13 IOR 0 R/W 5 PB5 IOR 0 R/W 12 PB12 IOR 0 R/W 4 PB4 IOR 0 R/W 11 PB11 IOR 0 R/W 3 PB3 IOR 0 R/W 10 PB10 IOR 0 R/W 2 PB2 IOR 0 R/W 9 PB9 IOR 0 R/W 1 PB1 IOR 0 R/W 8 PB8 IOR 0 R/W 0 PB0 IOR 0 R/W
RENESAS 407
14.3.4
Port B Control Registers (PBCR1 and PBCR2)
PBCR1 and PBCR2 are 16-bit read/write registers that select the functions of the sixteen multiplexed pins of port B. PBCR1 selects the function of the top eight bits of port B; PBCR2 selects the function of the bottom eight bits of port B. PBCR1 and PBCR2 are initialized to H'0000 by power-on resets but are not initialized for manual resets, standby mode, or sleep mode. PBCR1:
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 PB15 MD1 0 R/W 7 PB11 MD1 0 R/W 14 PB15 MD0 0 R/W 6 PB11 MD0 0 R/W 13 PB14 MD1 0 R/W 5 PB10 MD1 0 R/W 12 PB14 MD0 0 R/W 4 PB10 MD0 0 R/W 11 PB13 MD1 0 R/W 3 PB9 MD1 0 R/W 10 PB13 MD0 0 R/W 2 PB9 MD0 0 R/W 9 PB12 MD1 0 R/W 1 PB8 MD1 0 R/W 8 PB12 MD0 0 R/W 0 PB8 MD0 0 R/W
*
Bits 15 and 14 (PB15 mode (PB15MD1 and PB15MD0)): PB15MD1 and PB15MD0 select the function of the PB15/TP15/IRQ7 pin.
Bit 14: PB15MD0 0 1 Function Input/output (PB15) (initial value) Interrupt request input (IRQ7) Reserved Timing pattern output (TP15)
Bit 15: PB15MD1 0
1
0 1
*
Bits 13 and 12 (PB14 mode (PB14MD1 and PB14MD0)): PB14MD1 and PB14MD0 select the function of the PB14/TP14/IRQ6 pin.
Bit 12: PB14MD0 0 1 Function Input/output (PB14) (initial value) Interrupt request input (IRQ6) Reserved Timing pattern output (TP14)
Bit 13: PB14MD1 0
1
0 1
RENESAS 408
*
Bits 11 and 10 (PB13 mode (PB13MD1 and PB13MD0)): PB13MD1 and PB13MD0 select the function of the PB13/TP13/IRQ5/SCK1 pin.
Bit 10: PB13MD0 0 1 Function Input/output (PB13) (initial value) Interrupt request input (IRQ5) Serial clock input/output (SCK1) Timing pattern output (TP13)
Bit 11: PB13MD1 0
1
0 1
*
Bits 9 and 8 (PB12 mode (PB12MD1 and PB12MD0)): PB12MD1 and PB12MD0 select the function of the PB12/TP12/IRQ4/SCK0 pin.
Bit 8: PB12MD0 0 1 1 0 1 Function Input/output (PB12) (initial value) Interrupt request input (IRQ4) Serial clock input/output (SCK0) Timing pattern output (TP12)
Bit 9: PB12MD1 0
*
Bits 7 and 6: PB11 mode (PB11MD1 and PB11MD0): PB11MD1 and PB11MD0 select the function of the PB11/TP11/TxD1 pin.
Bit 6: PB11MD0 0 1 Function Input/output (PB11) (initial value) Reserved Transmit data output (TxD1) Timing pattern output (TP11)
Bit 7: PB11MD1 0
1
0 1
*
Bits 5 and 4 (PB10 mode (PB10MD1 and PB10MD0): PB10MD1 and PB10MD0 select the function of the PB10/TP10/RxD1 pin.
Bit 4: PB10MD0 0 1 Function Input/output (PB10) (initial value) Reserved Receive data input (RxD1) Timing pattern output (TP10)
Bit 5: PB10MD1 0
1
0 1
RENESAS 409
*
Bits 3 and 2 (PB9 mode (PB9MD1 and PB9MD0)): PB9MD1 and PB9MD0 select the function of the PB9/TP9/TxD0 pin.
Bit 2: PB9MD0 0 1 Function Input/output (PB9) (initial value) Reserved Transmit data output (TxD0) Timing pattern output (TP9)
Bit 3: PB9MD1 0
1
0 1
*
Bits 1 and 0 (PB8 mode (PB8MD1 and PB8MD0)): PB8MD1 and PB8MD0 select the function of the PB8/TP8/RxD0 pin.
Bit 0: PB8MD0 0 1 Function Input/output (PB8) (initial value) Reserved Receive data input (RxD0) Timing pattern output (TP8)
Bit 1: PB8MD1 0
1
0 1
PBCR2:
Bit: 15 14 13 12 11 10 9 8
Bit name: PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0
Bit name: PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD1 PB1MD0 PB0MD1 PB0MD0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
RENESAS 410
*
Bits 15 and 14 (PB7 mode (PB7MD1 and PB7MD0)): PB7MD1 and PB7MD0 select the function of the PB7/TP7/TOCXB4/TCLKD pin.
Bit 14: PB7MD0 0 1 Function Input/output (PB7) (initial value) ITU timer clock input (TCLKD) ITU output compare (TOCXB4) Timing pattern output (TP7)
Bit 15: PB7MD1 0
1
0 1
*
Bits 13 and 12 (PB6 mode (PB6MD1 and PB6MD0)): PB6MD1 and PB6MD0 select the function of the PB6/TP6/TOCXA4/TCLKC pin.
Bit 12: PB6MD0 0 1 Function Input/output (PB6) (initial value) ITU timer clock input (TCLKC) ITU output compare (TOCXA4) Timing pattern output (TP6)
Bit 13: PB6MD1 0
1
0 1
*
Bits 11 and 10 (PB5 mode (PB5MD1 and PB5MD0)): PB5MD1 and PB5MD0 select the function of the PB5/TP5/TIOCB4 pin.
Bit 10: PB5MD0 0 1 Function Input/output (PB5) (initial value) Reserved ITU input capture/output compare (TIOCB4) Timing pattern output (TP5)
Bit 11: PB5MD1 0
1
0 1
*
Bits 9 and 8 (PB4 mode (PB4MD1 and PB4MD0)): PB4MD1 and PB4MD0 select the function of the PB4/TP4/TIOCA4 pin.
Bit 8: PB4MD0 0 1 Function Input/output (PB4) (initial value) Reserved ITU input capture/output compare (TIOCA4) Timing pattern output (TP4)
Bit 9: PB4MD1 0
1
0 1
RENESAS 411
*
Bits 7 and 6 (PB3 mode (PB3MD1 and PB3MD0)): PB3MD1 and PB3MD0 select the function of the PB3/TP3/TIOCB3 pin.
Bit 6: PB3MD0 0 1 Function Input/output (PB3) (initial value) Reserved ITU input capture/output compare (TIOCB3) Timing pattern output (TP3)
Bit 7: PB3MD1 0
1
0 1
*
Bits 5 and 4 (PB2 mode (PB2MD1 and PB2MD0)): PB2MD1 and PB2MD0 select the function of the PB2/TP2/TIOCA3 pin.
Bit 4: PB2MD0 0 1 Function Input/output (PB2) (initial value) Reserved ITU input capture/output compare (TIOCA3) Timing pattern output (TP2)
Bit 5: PB2MD1 0
1
0 1
*
Bits 3 and 2 (PB1 mode (PB1MD1 and PB1MD0)): PB1MD1 and PB1MD0 select the function of the PB1/TP1/TIOCB2 pin.
Bit 2: PB1MD0 0 1 Function Input/output (PB1) (initial value) Reserved ITU input capture/output compare (TIOCB2) Timing pattern output (TP1)
Bit 3: PB1MD1 0
1
0 1
*
Bits 1 and 0 (PB0 mode (PB0MD1 and PB0MD0)): PB0MD1 and PB0MD0 select the function of the PB0/TP0/TIOCA2 pin.
Bit 0: PB0MD0 0 1 Function Input/output (PB0) (initial value) Reserved ITU input capture/output compare (TIOCA2) Timing pattern output (TP0)
Bit 1: PB0MD1 0
1
0 1
RENESAS 412
14.3.5
Column Address Strobe Pin Control Register (CASCR)
CASCR is a 16-bit read/write register that allows selection between column address strobe and chip select pin functions. The CASCR is initialized to H'5FFF by power-on resets but is not initialized for manual resets, standby mode, or sleep mode.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 CASH MD1 0 R/W 7 -- 1 -- 14 CASH MD0 1 R/W 6 -- 1 -- 13 CASL MD1 0 R/W 5 -- 1 -- 12 CASL MD0 1 R/W 4 -- 1 -- 11 -- 1 -- 3 -- 1 -- 10 -- 1 -- 2 -- 1 -- 9 -- 1 -- 1 -- 1 -- 8 -- 1 -- 0 -- 1 --
*
Bits 15 and 14 (CASH mode (CASHMD1 and CASHMD0)): CASHMD1 and CASHMD0 select the function of the CS1/CASH pin.
Bit 14: CASHMD0 0 1 Function Reserved Chip select output (CS1) (initial value) Column address strobe output (CASH) Reserved
Bit 15: CASHMD1 0
1
0 1
*
Bits 13 and 12 (CASL mode (CASLMD1 and CASLMD0)): CASLMD1 and CASLMD0 select the function of the CS3/CASL pin.
Bit 12: CASLMD0 0 1 Function Reserved Chip select output (CS3) (initial value) Column address strobe output (CASL) Reserved
Bit 13: CASLMD1 0
1
0 1
*
Bits 11-0 (reserved): This bit always reads as 1. The write value should always be 1.
RENESAS 413
Section 15 Parallel I/O Ports
15.1 Overview
There are two ports, A and B. Ports A and B are 16-bit I/O ports. The pins of the ports are all multiplexed for use as general-purpose I/Os or for other functions. (Use the pin function controller (PFC) to select the function of multiplexed pins.) Ports A and B each have one data register for storing pin data.
15.2
Port A
Port A is a 16-pin input/output port, as shown in figure 15.1. The PA3/CS7/WAIT pin of port A has a pull-up MOS so that when it is functioning as a WAIT pin, the wait state control register of the bus state controller can be used to select whether to pull up the WAIT pin or not. It is not pulled up when the pin is functioning as either PA3 or CS7.
Port A
PA15 (Input/output)/IRQ3 (Input)/DREQ1 (Input) PA14 (Input/output)/IRQ2 (Input)/DACK1 (Output) PA13 (Input/output)/IRQ1 (Input)/DREQ0 (Input)/TCLKB (Input) PA12 (Input/output)/IRQ0 (Input)/DACK0 (Output)/TCLKA (Input) PA11 (Input/output)/DPH (Input/output)/TIOCB1 (Input/output) PA10 (Input/output)/DPL (Input/output)/TIOCA1 (Input/output) PA9 (Input/output)/AH (Output)/IRQOUT (Output) PA8 (Input/output)/BREQ (Input) PA7 (Input/output)/BACK (Output) PA6 (Input/output)/RD (Output) PA5 (Input/output)/WRH (Output) (LBS (Output)) PA4 (Input/output)/WRL (Output) (WR (Output)) PA3 (Input/output)/CS7 (Output)/WAIT (Input) PA2 (Input/output)/CS6 (Output)/TIOCB0 (Input/output) PA1 (Input/output)/CS5 (Output)/RAS (Output) PA0 (Input/output)/CS4 (Output)/TIOCA0 (Input/output)
Figure 15.1 Port A Configuration 15.2.1 Register Configuration
Table 15.1 summarizes the port A register.
RENESAS 415
Table 15.1 Port A Register
Name Port A data register Abbreviation PADR R/W R/W Initial Value H'0000 Address H'5FFFFC0 Access Size 8, 16, 32
15.2.2
Port A Data Register (PADR)
PADR is a 16-bit read/write register that stores data for port A. The bits PA15DR-PA0DR correspond to the PA15/IRQ3/DREQ1-PA0/CS4/TIOCA0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PADR; when PADR is read, the register value will be output regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PADR is read. When a value is written to PADR, that value can be written into PADR, but it will not affect the pin status. Table 15.2 shows the read/write operations of the port A data register. PADR is initialized by a power-on reset. However, PADR is not initialized for manual reset, standby mode, or sleep mode.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 14 13 12 11 10 9 8
PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 PA3DR 0 R/W 0 R/W 2 0 R/W 1 0 R/W 0 PA0DR 0 R/W
PA7DR PA6DR 0 R/W 0 R/W
PA5DR PA4DR 0 R/W 0 R/W
PA2DR PA1DR 0 R/W 0 R/W
Table 15.2 Read/Write Operation of the Port A Data Register (PADR)
PAIOR 0 Pin Status Input Other function 1 Output Other function Read Pin status Pin status PADR value PADR value Write Can write to PADR, but it has no effect on pin status. Can write to PADR, but it has no effect on pin status. Value written is output by pin Can write to PADR, but it has no effect on pin status.
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15.3
Port B
Port B is a 16-bit input/output port as shown in figure 16.2.
Port B
PB15 (Input/output)/TP15 (Output)/IRQ7 (Input) PB14 (Input/output)/TP14 (Output)/IRQ6 (Input) PB13 (Input/output)/TP13 (Output)/IRQ5 (Input)/SCK1 (Input/output) PB12 (Input/output)/TP12 (Output)/IRQ4 (Input)/SCK0 (Input/output) PB11 (Input/output)/TP11 (Output)/TxD1 (Output) PB10 (Input/output)/TP10 (Output)/RxD1 (Input) PB9 (Input/output)/TP9 (Output)/TxD0 (Output) PB8 (Input/output)/TP8 (Output)/RxD0 (Input) PB7 (Input/output)/TP7 (Output)/TOCXB4 (Output)/TCLKD (Input) PB6 (Input/output)/TP6 (Output)/TOCXA4 (Output)/TCLKC (Input) PB5 (Input/output)/TP5 (Output)/TIOCB4 (Output) PB4 (Input/output)/TP4 (Output)/TIOCA4 (Output) PB3 (Input/output)/TP3 (Output)/TIOCB3 (Input/output) PB2 (Input/output)/TP2 (Output)/TIOCA3 (Input/output) PB1 (Input/output)/TP1 (Output)/TIOCB2 (Input/output) PB0 (Input/output)/TP0 (Output)/TIOCA2 (Input/output)
Figure 15.2 Port B Configuration 15.3.1 Register Configuration
Table 15.3 summarizes the port B register. Table 15.3 Port B Register
Name Port B data register Abbreviation PBDR R/W R/W Initial Value H'0000 Address H'5FFFFC2 Access Size 8, 16, 32
RENESAS 417
15.3.2
Port B Data Register (PBDR)
PBDR is a 16-bit read/write register that stores data for port B. The bits PB15DR-PB0DR correspond to the PB15/TP15/IRQ7-PB0/TP0/TIOCA2 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PBDR; when PBDR is read, the register value will be output regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PBDR is read. When a value is written to PBDR, that value can be written into PBDR, but it will not affect the pin status. When the pin function is set to timing pattern output and the TPC output is enabled by the TPC next data enable register (NDER), no value can be written to PBDR. Table 15.4 shows the read/write operations of the port B data register. PBDR is initialized by a power-on reset. However, PBDR is not initialized for a manual reset, standby mode, or sleep mode.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 14 13 12 11 10 9 8
PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR PB8DR 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 PB3DR 0 R/W 0 R/W 2 0 R/W 1 0 R/W 0 PB0DR 0 R/W
PB7DR PB6DR 0 R/W 0 R/W
PB5DR PB4DR 0 R/W 0 R/W
PB2DR PB1DR 0 R/W 0 R/W
Table 15.4 Read/Write Operation of the Port B Data Register (PBDR)
PBIOR 0 Pin Status Input TPn Other function 1 Output TPn Other function Read Pin status Pin status Pin status PBDR value PBDR value PBDR value Write Can write to PBDR, but it has no effect on pin status Disabled Can write to PBDR, but it has no effect on pin status Value written is output by pin Disabled Can write to PBDR, but it has no effect on pin status
TPn: Timing pattern output
RENESAS 418
Section 16 ROM
16.1 Overview
The SH7020 microcomputer has 16 kbytes of on-chip ROM (mask ROM). The SH7021 microcomputer has 32 kbytes of on-chip ROM (mask ROM or PROM). The on-chip ROM is connected to the CPU and the direct memory access controller (DMAC) through a 32-bit data bus (figure 16.1). The CPU can access the on-chip ROM in 8-, 16- and 32-bit widths and the DMAC can access the ROM in 8- and 16-bit widths. Data in the on-chip ROM can always be accessed in one cycle.
RENESAS 419
SH7020 Internal data bus (32 bits)
H'0000000 H'0000004
H'0000001 H'0000005
H'0000002 H'0000006
H'0000003 H'0000007
On-chip ROM H'0003FFC SH7021 Internal data bus (32 bits) H'0003FFD H'0003FFE H'0003FFF
H'0000000 H'0000004
H'0000001 H'0000005
H'0000002 H'0000006
H'0000003 H'0000007
On-chip ROM H'0007FFC Note: H'0007FFD H'0007FFE H'0007FFF
The addresses shown in the figure are the first shadow addresses in the on-chip ROM space.
Figure 16.1 Block Diagram of ROM The operating mode determines whether the on-chip ROM is valid or not. The operating mode is selected using mode-setting pins MD0-MD2 as shown in table17.1. If you are using the on-chip ROM, select mode 2; if you are not, select mode 0 or 1. The on-chip ROM is allocated to address H'0000000-H'0003FFF (SH7020), H'0000000-H'0007FFF (SH7021) of memory area 0. Memory area 0 (H'0000000-H'0FFFFFF and H'8000000-H'8FFFFFF) is divided into 16-kbyte (SH7020) or 32-kbyte (SH7021) shadows. No matter which shadow is accessed, the on-chip ROM is accessed. See section 8, Bus State Controller, for more information on shadows.
420 RENESAS
Table 16.1 Operating Modes and ROM
Mode Setting Pin Operating Mode Mode 0 (MCU mode 0) Mode 1 (MCU mode 1) Mode 2 (MCU mode 2) Mode 7 (PROM mode) 0: Low 1: High MD2 0 0 0 1 MD1 0 0 1 1 MD0 0 1 0 1 Area 0 On-chip ROM invalid, external 8-bit space On-chip ROM invalid, external 16-bit space On-chip ROM valid --
When the SH7021 is set to PROM mode, the PROM version can write programs exactly like ordinary EPROM using a general purpose EPROM writer.
16.2
16.2.1
PROM Mode
Setting the PROM Mode
To program the on-chip PROM, set the pins as shown in figure 16.2 and use the chip in PROM mode. 16.2.2 Socket Adapter Pin Correspondence and Memory Map
Mount the socket adapter to the SH7021 as shown in figure 16.2. This allows the on-chip PROM to be programmed in exactly the same way as ordinary 32-pin EPROMs (HN27C101). Figure 16.2 shows the correspondence of SH7021 pins and HN27C101 pins. Figure 16.3 shows the memory map of the on-chip ROM. The address range of the HN27C101 (128 kbytes) is H'00000-H'1FFFF. The on-chip PROM (34 kbytes) is not found in H'08000-H'1FFFF. When programming with a PROM writer, the program address range must be set to H'00000- H'07FFF. The data for the H'08000-H'1FFFF address area should all be H'FF. Set byte mode, not page mode.
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SH7021 Pin Name Pin Number 76 RES 74 NMI 1 AD0 2 AD1 3 AD2 5 AD3 6 AD4 7 AD5 8 AD6 9 AD7 20 A0/HBS 21 A1 22 A2 23 A3 25 A4 26 A5 27 A6 28 A7 29 A8 30 A9 31 A10 33 A11 34 A12 35 A13 36 A14 37 A15 39 A16 53 PA2/CS6/TIOCB0 54 PA3/CS7/WAIT 40 A17 42 A18 VCC 13, 38, 63, 73, 80, 88 77 MD0 78 MD1 79 MD2 4, 15, 24, 32, 41, VSS 50, 59, 70, 81, 82,92 Pin other than the above NC (release)
EPROM Socket HN27C101 Adapter Pin Name Pin Number VPP 1 A9 26 I/O0 13 I/O1 14 I/O2 15 I/O3 17 I/O4 18 I/O5 19 I/O6 20 I/O7 21 A0 12 A1 11 A2 10 A3 9 A4 8 A5 7 A6 6 A7 5 A8 27 24 OE A10 23 A11 25 A12 4 A13 28 A14 29 A15 3 A16 2 31 PGM 22 CE VCC 32 VSS 16 * VPP: PROM program power adapter * A16-A0: Address input * I/O7-I/O0: Data input/ output * OE: Output enable * PGM: Program enable * CE: Chip enable
Figure 16.2 Correspondence Between SH7021 Pins and HN27C101 Pins
422 RENESAS
Addresses in MCU modes 0, 1, and 2* H'0000000
Addresses in PROM mode H'0000
On-chip ROM space (area 0)
H'0007FFF
H'7FFF
Note: Addresses in the figure are the uppermost shadow addresses of the on-chip ROM space.
Figure 16.3 Memory Map of On-chip ROM
16.3
PROM Programming
The write/verify specifications in PROM mode are the same as for the standard EPROM HN27C101. The page program system is not supported, so do not set the PROM writer to the page programming mode. Naturally, PROM writers that only support the page programming mode cannot be used. When selecting a PROM writer, check that the high-speed, high-reliability programming system for each byte is supported. 16.3.1 Selecting the Programming Mode
There are two on-chip PROM programming modes: write and verify (which reads and confirms the data written). Use the pins to select the modes (table 16.2).
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Table 16.2 Select PROM Programming Mode
Pin Mode Write Verify Program inhibit CE 0 0 0 0 1 1 Symbols: 0: Low 1: High VPP: VPP level VCC: VCC level OE 1 0 0 1 0 1 PGM 0 1 0 1 0 1 VPP VPP VCC VCC I/O7-I/O0 Data input Data output High impedance A16-A0 Address input
16.3.2
Write/Verify and Electrical Characteristics
Write/Verify: Write/verify can be accomplished by an efficient high-speed high-reliability programming system. This system can write data quickly and accurately without placing voltage stress on the device. The basic flowchart for this high-speed, high-reliability programming system is shown in figure 16.4.
424 RENESAS
Start Set EPROM writer to write/verify mode (VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V) Address = 0 n=0 n+1n Data write (tPW = 0.2 ms 5%) Verify result OK? Yes Data write (tOPW = (0.2 x n) ms) Final address? Yes Set EPROM writer to read mode (VCC = 5.0 V 0.25 V, VPP = VCC) Address + 1 Address
No Yes n = 25?
No
No
No good VCC: VPP: tPW: tOPW: Power supply PROM program power supply Initial programming pulse width Over programming pulse width
No
Results of reading all address OK? Yes End
Figure 16.4 Basic Flowchart of High-Speed High-Reliability Programming
RENESAS 425
Electrical Characteristics: Tables 16.3 and 16.4 show the electrical characteristics of programming. Figure 16.5 shows the timing. Table 16.3 DC Characteristics (VCC = 6.0 V 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V, Ta = 25 5C)
Item Input high voltage Input low voltage Output high voltage Output low voltage Input leak current VCC current VPP current Pins I/O7-I/O0, A16-A0, OE, CE, PGM I/O7-I/O0, A16-A0, OE, CE, PGM I/O7-I/O0 I/O7-I/O0 I/O7-I/O0, A16-A0, OE, CE, PGM Symbol VIH VIL VOH VOL |ILI| I CC I PP Min 2.4 -0.3 2.4 -- -- -- -- Typ Max -- -- -- -- -- -- -- Unit Measurement Conditions
VCC + 0.3 V 0.8 -- 0.45 2 40 40 V V V A mA mA I OH = -200 A I OL = 1.6 mA VIN = 5.25 V/0.5 V
426 RENESAS
Table 16.4 AC Characteristics (VCC = 6.0 V 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V, Ta = 25 5C)
Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time PGM pulse width in initial programming PGM pulse width in over programming VCC setup time CE setup time Data output delay time Symbol t AS t OES t DS t AH t DH t DF*2 t VPS t PW t OPW * 3 t VCS t CES t OE Min 2 2 2 0 2 -- 2 0.19 0.19 2 2 0 Typ -- -- -- -- -- -- -- 0.20 -- -- -- -- Max -- -- -- -- -- 130 -- 0.21 5.25 -- -- 150 Unit s s s s s ns s ms ms s s ns Measurement Conditions Figure 16.5*1
Notes: 1. Input pulse level: 0.45-2.4 V Input rise, fall time 20 ns Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V 2. t DF is defined as when output reaches the release state and the output level could not be referenced. 3. t OPW is defined as the value given in the flowchart.
RENESAS 427
Write Address tAS Data tDS VPP VPP VCC VCC + 1 VCC CE tCES PGM tPW (tOPW) OE tOES tOE tVCS tVPS Write data tDH
Verify
tAH Read data tDF
VCC
Note: t OPW is defined as the value given in the flowchart.
Figure 16.5 Write/Verify Timing 16.3.3 Points to Note About Writing
1. Always write using the prescribed voltage and timing. The write voltage (programming voltage) VPP is 12.5 V (when the EPROM writer is set to the Hitachi specifications for HN27C101, VPP becomes 12.5 V.) Applying a voltage in excess of the rated voltage may damage the device. Pay particular attention to overshooting in the EPROM writer. 2. Before programming, always check that the indexes of the EPROM writer socket, socket adapter, and devices are consistent with each other. If they are not mounted in the proper location, an overcurrent may be generated, damaging the device. 3. Do not touch the socket adapter or device during writing. Contact can cause malfunctions that prevent data from being written accurately.
428 RENESAS
4. You cannot write in the page programming mode. Always set the equipment to the byte programming mode. 5. The capacity of the on-chip ROM is 32 kbytes, so the data of PROM writer addresses H'08000-H'1FFFF should be H'FF. Always set the range for PROM addresses to H'0000- H'7FFF. 6. When write errors occur on consecutive addresses, stop writing. Check to see if there are any abnormalities in the EPROM writer and socket adapter. 16.3.4 Reliability After Writing
After programming, we recommend letting the device stand at high temperature (125-150C) for 24-48 hours to increase the reliability of data retention. Letting it stand at high temperature is a type of screening method that can get rid of initial data retention defects of the on-chip PROM's memory cell within a short period of time. Figure 16.6 shows the flow from programming of the on-chip PROM, including screening, to mounting on the device board.
Writing and verification of program
Flow chart from figure 16.4
Let stand in nonconductive, high temperature environment (125-150C, 24-48 hours)
Data read and verification (VCC = 5.0 V)
Mount on board
Figure 16.6 Screening Flow If abnormalities are found when the program is written and verified or the program is read and checked after the writing/verification or letting the chip stand at high temperature, contact Hitachi's engineering departments.
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Section 17 RAM
17.1 Overview
The SH7020 and SH7021 has 1-kbytes of on-chip RAM. The on-chip RAM is linked to the CPU and direct memory access controller (DMAC) with a 32-bit data bus (figure 17.1). The CPU can access data in the on-chip RAM in byte, word, or long word units. The DMAC can access byte or word data. On-chip RAM data can always be accessed in one state, making the RAM ideal for use as a program area, stack area, or data area, which require high-speed access. The contents of the on-chip RAM are held in both the sleep and standby modes. Memory area 7 addresses H'FFFFC00 to H'FFFFFFF are allocated to the on-chip RAM.
Internal data bus (32 bits)
H'FFFFC00 H'FFFFC04
H'FFFFC01 H'FFFFC05
H'FFFFC02 H'FFFFC06
H'FFFFC03 H'FFFFC07
On-chip RAM H'FFFFFFC H'FFFFFFD H'FFFFFFE H'FFFFFF
Figure 17.1 Block Diagram of RAM
17.2
Operation
Accesses to addresses H'FFFFC00-H'FFFFFFF are directed to the on-chip RAM. Memory area 7 (H'F000000-H'FFFFFFF) is divided into shadows in 1 kbyte units. All shadow accesses are onchip RAM accesses. For more information on shadows, see section 8, Bus State Controller.
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Section 18 Power-Down States
18.1 Overview
In the power-down mode, all CPU functions are halted. This lowers power consumption dramatically. 18.1.1 Power-Down Modes
The SH microprocessor has two power-down modes. 1. Sleep mode 2. Standby mode The sleep mode and standby mode are entered from the program execution state according to the transition conditions given in table 18.1. Table 18.1 also describes procedures for canceling each mode and the states of the CPU and peripheral functions. Table 18.1 Power-Down States
State Mode Sleep mode Entering Procedure Execute SLEEP instruction with SBY bit set to 0 in SBYCR Clock Run CPU Halt Peripheral Functions Run CPU Registers RAM Held Held I/O Ports Held Canceling Procedure * Interrupt * DMA address error * Power-on reset * Manual reset * NMI * Power-on reset * Manual reset
Standb y mode
Execute SLEEP instruction with SBY bit set to 1 in SBYCR
Halt
Halt
Halt*1
Held
Held
Held or high-Z*2
SBYCR: Standby control register SBY: Standby bit Notes: 1. Some of the registers of the on-chip peripheral modules are not initialized in the standby mode. For details, see table 18.3, Status of Registers in the Standby Mode in section 18.4.1, Transition to the Standby Mode, or the descriptions of registers given where the on-chip peripheral modules are covered. 2. The status of I/O ports in the standby mode are set by the port high-impedance bit (HIZ) of the SBYCR. See section 18.2, Standby Control Register (SBYCR) for details. The status of pins other than the I/O ports are described in appendix B, Pin States. RENESAS 433
18.1.2
Register
Table 18.2 summarizes the register related to the power-down state. Table 18.2 Standby Control Register (SBYCR)
Name Standby control register Abbreviation SBYCR R/W R/W Initial Value H'1F Address H'5FFFFBC Access size 8, 16, 32
18.2
Standby Control Register (SBYCR)
The standby control register (SBYCR) is an 8-bit register that can be read or written to. It is set in order to enter the standby mode and also sets the port states in standby mode. The SBYCR is initialized to H'1F when reset.
Bit: Bit name: Initial value: R/W: 7 SBY 0 R/W 6 HIZ 0 R/W 5 -- 0 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
*
Bit 7 (standby (SBY)): SBY enables transition to the standby mode. The SBY bit cannot be set to 1 while the timer enable bit (bit TME) in timer control/status register TCSR of watchdog timer WDT is set to 1. To enter the standby mode, clear the TME bit to 0 to halt the WDT and set the SBY bit.
Description Executing SLEEP instruction puts the LSI into sleep mode (initial value) Executing SLEEP instruction puts the LSI into standby mode
SBY 0 1
*
Bit 6 (port high-impedance (HIZ)): HIZ selects whether I/O ports remain in their previous states during standby, or are placed in the high-impedance state when the standby mode is entered. The HIZ bit cannot be set to 1 while the TME bit is set to 1. To place the pins of the I/O ports in high impedance, clear the TME bit to 0 before setting the HIZ bit.
Description Port states are maintained during standby (initial value) Ports are placed in the high-impedance state in standby
HIZ 0 1
RENESAS 434
*
Bits 5-0 (reserved): Bit 5 is a read-only bit that always reads as 0. Only write 0 to bit 5. Writing to bits 4-0 is disabled. These bits always read 1.
18.3
18.3.1
Sleep Mode
Transition to the Sleep Mode
Execution of the SLEEP instruction when the standby bit (SBY) in the standby control register (SBYCR) is cleared to 0 causes a transition from the program execution state to the sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules do not halt in the sleep mode. 18.3.2 Canceling the Sleep Mode
The sleep mode is canceled by an interrupt, DMA address error, power-on reset, or manual reset. Cancellation by an Interrupt: When an interrupt occurs, the sleep mode is canceled and interrupt exception processing is executed. The sleep mode is not canceled if the interrupt cannot be accepted because its priority level is equal to or less than the mask level set in the CPU's status register (SR). Likewise, the sleep mode is not canceled if the interrupt is disabled by the on-chip peripheral module. Cancellation by a DMA Address Error: If the DMAC operates during the sleep mode and a DMA address error occurs, the sleep mode is canceled and DMA address error exceptionprocessing is executed. Cancellation by a Power-On Reset: If the RES signal goes low while the NMI signal is high, the sleep mode is canceled and the power-on reset state is entered. If the NMI signal is brought from low to high in order to set the LSI for power-on resets, an NMI interrupt will occur whenever the rising edge of the NMI is selected as the valid edge (in NMI edge select bit NMIE of the interrupt control register ICR of the interrupt controller). When this occurs, the NMI interrupt cancels the sleep mode. Cancellation by a Manual Reset: If the RES signal goes low while the NMI signal is low, the sleep mode is canceled and the manual reset state is entered. If the NMI signal is brought from high to low in order to set the LSI for manual resets, the sleep mode will be canceled by an NMI interrupt whenever the falling edge of the NMI is selected as the valid edge (in the NMIE bit).
RENESAS 435
18.4
18.4.1
Standby Mode
Transition to the Standby Mode
To enter the standby mode, set the standby bit (SBY) to 1 in the standby control register (SBYCR), then execute the SLEEP instruction. The LSI moves from the program execution state to the standby mode. The standby mode greatly reduces power consumption by halting not only the CPU, but the clock and on-chip peripheral modules as well. Some registers of the on-chip peripheral modules are initialized, others are not (See table 18.3). As long as the specified voltage is supplied, however, CPU register contents and on-chip RAM data are held. The I/O port state (hold or high impedance) depends on the port high-impedance bit (HIZ) in the SBYCR. For details on the states of these pins, see appendix B. Pin States.
RENESAS 436
Table 18.3 Register States in the Standby Mode
Module Interrupt controller (INTC) User break controller (UBC) Bus state controller (BSC) Pin function controller (PFC) I/O ports Direct memory access controller (DMAC) Watchdog timer (WDT) Register Initialized -- -- -- -- -- All registers * Bits 7-5 (OVF, WT/IT, TME) of the timer control status register (TCSR) * Reset control/status register (RSTCSR) 16-bit integrated timer pulse unit (ITU) Programmable timing pattern controller (TPC) Serial communications interface (SCI) All registers -- * Receive data register (RDR) * Transmit data register (TDR) * Serial mode register (SMR) * Serial control register (SCR) * Serial status register (SSR) * Bit rate register (BBR) Power-down state register -- Standby control register (SBYCR) Registers That Hold Data All registers All registers All registers All registers All registers -- * Bits 2-0 (CKS2-CKS0) of the timer control status register (TCSR) * Timer counter (TCNT) -- All registers --
RENESAS 437
18.4.2
Canceling the Standby Mode
The standby mode is canceled by an NMI interrupt, a power-on reset, or a manual reset. Cancellation by an NMI: When a rising edge or falling edge (as selected by the NMIE bit in interrupt control register ICR of interrupt controller INTC) is detected at the NMI pin, the clock oscillator begins operating. At first, clock pulses are supplied only to the watchdog timer. After the time that was selected before entering the standby mode using clock select bits 2-0 (CKS2-CKS0) in the timer control/status register TCSR of the watchdog timer WDT, the watchdog timer overflows. After the overflow, the clock is considered stable and supplied to the entire chip. The standby mode is canceled and the NMI exception-processing sequence begins. When the standby mode is cleared by an NMI interrupt, bits CKS2-CKS0 must be set so that the WDT overflow interval is equal to or greater than the clock settling time. When the standby mode is cleared when the fall edge has been selected in the NMI bit, be sure that the NMI pin is high when standby is entered (when the clock is halted) and low when the chip returns from standby (clock starts up after oscillator is stabilized). Likewise, when the standby mode is cleared when the rise edge has been selected in the NMI bit, be sure that the NMI pin is low when standby is entered (clock halted) and high when the chip returns from standby (clock starts up after oscillator is stabilized). Cancellation by a Power-On Reset: If the RES signal goes low while the NMI signal is high, the standby mode is canceled and the power-on reset state is entered. If the NMI signal is brought from low to high in order to set the LSI for power-on resets, the standby mode will not be canceled by an NMI interrupt, because the NMI signal is initialized for the falling edge in the standby mode (by the NMIE bit). Cancellation by a Manual Reset: If the RES signal goes low while the NMI signal is low, the standby mode is canceled and the manual reset state is entered. If the NMI signal is brought from high to low in order to set the LSI for manual resets, the standby mode will first be canceled by an NMI interrupt, because the NMI signal is initialized for the falling edge in the standby mode (by the NMIE bit).
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18.4.3
Standby Mode Application
In this example, the standby mode is entered on the falling edge of the NMI signal and canceled on the rising edge of the NMI signal. Figure 18.1 shows the timing. After an NMI interrupt is accepted (high goes to low) while the NMI edge select bit NMIE in the interrupt control register ICR is cleared to 0 to select detection of the falling edge, the NMI exception service routine sets the NMIE to 1 (selecting detection of the rising edge) and sets the SBY bit to 1. Finally, it executes a SLEEP instruction to enter the standby mode. The standby mode is canceled on the rising edge of the NMI signal.
Oscillator
CK
NMI
NMIE
SSBY Clock setting time
NMI Exception exception service processing routine SBY = 1 SLEEP instruction
Standby Oscillation mode start time
Time set in WDT
NMI exception processing
Figure 18.1 NMI Timing for the Standby Mode (Example)
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Section 19 Electrical Characteristics
19.1 Absolute Maximum Ratings
Table 19.1 Absolute Maximum Ratings
Item Power supply voltage Program voltage Input voltage Operating temperature Storage temperature Symbol VCC VPP Vin Topr Tstg Rating -0.3 to +7.0 -0.3 to +13.5 -0.3 to VCC + 0.3 -20 to +75* -55 to +125 Unit V V V C C
Caution: Operating the LSI in excess of the absolute maximum rating may result in permanent damage. Note: Normal Products: Topr = -40 to +85C for wide-temperature range products
RENESAS 441
19.2
DC Characteristics
Table 19.2 lists DC characteristics. Table 19.3 lists the permissible output current values. Usage Conditions: * The current consumption value is measured under conditions of V IH min = VCC - 0.5 V and VIL max = 0.5 V with no load on any output pin and the on-chip pull-up MOS off.
Table 19.2 DC Characteristics (1) Conditions: VCC = 5.0 V 10%, V SS = 0 V, = 20 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
Item Input highlevel voltage Input lowlevel voltage Schmidt trigger input voltage Input leak current 3-state leak current (while off) Input pullup MOS current Output high-level voltage RES, NMI, MD2-MD0 EXTAL Other input pins RES, NMI, MD2-MD0 Other input pins PA13-PA10, PA2, PA0, PB7- PB0 VT+ VT- |Iin| VIL Symbol Min VIH Typ Max Measurement Unit Conditions
VCC - 0.7-- VCC x 0.7-- 2.2 -0.3 -0.3 4.0 -- -- -- -- -- -- -- -- -- --
VCC + 0.3 V VCC + 0.3 V VCC + 0.3 V 0.5 0.8 -- 1.0 -- 1.0 1.0 1.0 V V V V V A A A Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to VCC - 0.5 V
VT+-VT- 0.4 RES NMI, MD2-MD0 Ports A and B, CS3-CS0, A21- A0, AD15-AD0 PA3 |ITSI| -- -- --
-Ip
20
--
300
A
Vin = 0V
All output pins
VOH
VCC - 0.5-- 3.5 --
-- --
V V
I OH = -200 A I OH = -1 mA
RENESAS 442
Table 19.2 DC Characteristics (1) (cont) Conditions: VCC = 5.0 V 10%, V SS = 0 V, = 20 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products .
Item Output low level voltage Input capacitance All output pins Symbol Min Typ Max VOL Cin -- -- RES NMI All other input pins Current consumption Ordinary operation I CC -- -- -- -- -- -- Sleep -- -- -- Standby -- -- RAM stand-by voltage VRAM 2.0 -- -- -- -- -- 65 75 90 30 35 40 0.4 1.2 30 30 20 80 90 100 50 55 60 Measurement Unit Conditions V V pF pF pF mA mA mA mA mA mA A A V I OL = 1.6 mA I OL = 8 mA Vin = 0 V Input signal f = 1 MHz Ta = 25C f = 12.5 MHz f = 16.6 MHz f = 20 MHz f = 12.5 MHz f = 16.6 MHz f = 20 MHz Ta 50C 50C < Ta
0.01 5 -- -- 20.0 --
Usage Notes: 1. Current dissipation values are for VIH min = VCC - 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 5. The ZTAT and mask versions have the same functions, and the electrical characteristics of both are within specification, but characteristic-related performance values, operating margins, noise margins, noise emission, etc., are different. Caution is therefore required in carrying out system design, and when switching between ZTAT and mask versions.
RENESAS 443
Table 19.2 DC Characteristics (2) Conditions: VCC = 5.0 V 10%, V SS = 0 V, = 16.6 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
Item Input highlevel voltage RES, NMI, MD2-MD0 EXTAL Other input pins Input lowlevel voltage RES, NMI, MD2-MD0 Other input pins Schmidt trigger input voltage Input leak current PA13-10, PA2, PA0, PB7-PB0 VT VT
+ -
Symbol Min VIH
Typ Max VCC + 0.3 VCC + 0.3 VCC + 0.3 0.5 0.8 -- 1 -- 1.0 1.0 1.0
Measurement Unit Conditions V V V V V V V V A A A Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to VCC - 0.5 V Vin = 0 V I OH = -200 A I OH = -1 mA I OL = 1.6 mA I OL = 8 mA
VCC - 0.7 -- VCC x 0.7 -- 2.2 -- -- -- -- -- -- -- -- --
VIL
-0.3 -0.3 4.0 -- 0.4 -- --
VT+-VT- RES NMI, MD2-MD0 |Iin|
3-state leak Ports A and B, current (while CS3-CS0, A21- off) A0, AD15-AD0 Input pull-up PA3 MOS current Output highlevel voltage Output low level voltage All output pins
|ITSI|
--
-Ip VOH VOL
20
--
300 -- -- 0.4 1.2
A V V V V
VCC - 0.5 -- 3.5 -- -- -- -- --
All output pins
RENESAS 444
Table 19.2 DC Characteristics (2) (cont) Conditions: VCC = 5.0 V 10%, V SS = 0 V, = 16.6 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products .
Item Input capacitance RES NMI All other input pins Current consumption Ordinary operation I CC Symbol Cin Min -- -- -- -- -- Sleep -- -- Standby -- -- RAM stand-by voltage VRAM 2.0 Typ -- -- -- 65 75 30 35 0.01 -- -- Max 30 30 20 80 90 50 55 5 20.0 -- Unit pF pF pF mA mA mA mA A A V Measurement Conditions Vin = 0 V Input signal f = 1 MHz Ta = 25C f = 12.5 MHz f = 16.6 MHz f = 12.5 MHz f = 16.6 MHz Ta 50C 50C < Ta
RENESAS 445
Table 19.2 DC Characteristics (3) Conditions: VCC = 3.0 V to 5.5 V, VSS = 0 V, = 12.5 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
Item Input highlevel voltage RES, NMI, MD2-MD0 EXTAL Other input pins Input lowlevel voltage RES, NMI, MD2-MD0 Other input pins Schmidt trigger PA13-10, PA2, input PA0, PB7-PB0 voltage VT
+
Symbol Min VIH VCC x 0.9 VCC x 0.7 VCC x 0.7 VIL -0.3 -0.3 VCC x 0.9 --
Typ Max -- -- -- -- -- -- -- VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC x 0.1 VCC x 0.2 -- VCC x 0.2 -- 1.0 1.0 1.0
Measurement Unit Conditions V V V V V V V V A A A Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to VCC - 0.5 V Vin = 0V I OH = -200 A I OH = -1 mA I OL = 1.6 mA I OL = 8 mA
VT- VT+-VT- |Iin|
VCC x 0.07 -- -- -- -- -- --
Input leak current
RES NMI, MD2-MD0
3-state leak Ports A and B, current (while CS3-CS0, A21- off) A0, AD15-AD0 Input pull-up MOS current Output highlevel voltage Output low level voltage PA3 All output pins
|ITSI|
--
-Ip VOH VOL
20 VCC - 0.5 VCC - 1.0 -- --
-- -- -- -- --
300 -- -- 0.4 1.2
A V V V V
All output pins
RENESAS 446
Table 19.2 DC Characteristics (3) (cont) Conditions: VCC = 3.0 V to 5.5 V, VSS = 0 V, = 12.5 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products .
Item Input capacitance RES NMI All other input pins Current consumption Ordinary operation Sleep Standby I CC Symbol Cin Min -- -- -- -- -- -- -- RAM stand-by voltage VRAM 2.0 Typ -- -- -- 65 30 0.01 -- -- Max 30 30 20 80 50 5.0 20 -- Unit pF pF pF mA mA A A V Measurement Conditions Vin = 0 V Input signal f = 1 MHz Ta = 25C f = 12.5 MHz f = 12.5 MHz Ta 50C 50C < Ta
RENESAS 447
Table 19.3 Permitted Output Current Values Case A: V CC = 3.0 to 5.5 V, VSS = 0 V, = 12.5 MHz, Ta = -20 to +75C* Case B: VCC = 5.0 V 10%, V SS = 0 V, = 16.6 MHz, Ta = -20 to +75C* Case C: VCC = 5.0 V 10%, V SS = 0 V, = 20 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
12.5 MHz Item Output low-level permissible current (per pin) Output low-level permissible current (total) Output high-level permissible current (per pin) Output high-level permissible current (total) Symbol I OL IOL -I OH - IOH Min -- -- -- -- Typ -- -- -- -- Max 10 80 2.0 25 Unit mA mA mA mA
Caution: To ensure LSI reliability, do not exceed the value for output current given in table 19.3.
RENESAS 448
19.3
AC Characteristics
The following AC timing chart represents the AC characteristics, not signal functions. For signal functions, see the explanation in the text. 19.3.1 Clock Timing
Table 19.4 Clock Timing Case A: V CC = 3.0 to 5.5 V, VSS = 0 V, Ta = -20 to +75C* Case B: VCC = 5.0 V 10%, V SS = 0 V, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
Case A Sym- 12.5 MHz bol Min Max t EXH t EXL t EXr t EXf t cyc t CH t CL t Cr t Cf 20 20 -- -- 80 30 30 -- -- -- -- 10 10 -- -- -- 10 10 -- -- Case B 16.6 MHz Min 10 10 -- -- 60 20 20 -- -- 10 10 Max -- -- 5 5 500 -- -- 5 5 -- -- 20 MHz Min 10 10 -- -- 50 20 20 -- -- 10 10 Max -- -- 5 5 500 -- -- 5 5 -- -- Unit ns ns ns ns ns ns ns ns ns ms ms 19.3 19.1, 19.2 19.2 Figures 19.1
Item EXTAL input high level pulse width EXTAL input low level pulse width EXTAL input rise time EXTAL input fall time Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Reset oscillation settling time Software standby oscillation settling time
t OSC1 10 t OSC2 10
RENESAS 449
tcyc tEXH tEXL
1/2 VCC EXTAL VIL
VIH
tEXr
tEXf
Figure 19.1 EXTAL Input Timing
tCYC tCH CK tCf tCr tCL
Figure 19.2 System Clock Timing
CK VCC tOSC1 RES
tOSC2
Figure 19.3 Oscillation Settling Time
RENESAS 450
19.3.2
Control Signal Timing
Table 19.5 Control Signal Timing Case A: V CC = 3.0 to 5.5 V, VSS = 0 V, Ta = -20 to +75C* Case B: VCC = 5.0 V 10%, V SS = 0 V, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
Case A 12.5 MHz Item RES setup time RES pulse width NMI reset setup time NMI reset hold time NMI setup time NMI hold time IRQ0-IRQ7 setup time (edge detection time) IRQ0-IRQ7 setup time (level detection time) IRQ0-IRQ7 hold time IRQOUT output delay time) Bus request setup time Bus acknowledge delay time 1 Bus acknowledge delay time 2 Bus 3-state delay time Symbol Min t RESS t RESW t NMIRS t NMIRH t NMIS t NMIH t IRQES t IRQLS t IRQEH t IRQOD t BRQS t BACD1 t BACD2 t BZD 320 20 320 320 160 80 160 160 80 -- 80 -- -- -- Max -- -- -- -- -- -- -- -- -- 80 -- 80 80 80 Case B 16.6 MHz Min 240 20 240 240 120 60 120 120 60 -- 60 -- -- -- Max -- -- -- -- -- -- -- -- -- 60 -- 60 60 60 20 MHz Min 200 20 200 200 100 50 100 100 50 -- 50 -- -- -- Max -- -- -- -- -- -- -- -- -- 50 -- 50 50 50 Unit ns t cyc ns ns ns ns ns ns ns ns ns ns ns ns 19.6 19.7 19.5 Figure 19.4
RENESAS 451
CK tRESS RES tNMIRS NMI tRESW tNMIRH tRESS
Figure 19.4 Reset Input Timing
CK tNMIS NMI tIRQES tIRQEH tNMIH
IRQ edge tIRQLS
IRQ level
Figure 19.5 Interrupt Signal Input Timing
RENESAS 452
CK tIRQOD tIRQOD
IRQOUT
Figure 19.6 Interrupt Signal Output Timing
CK tBRQS BREQ (Input) BACK (Output) tBZD RD, WR, RAS, CAS, CSn tBRQS tBACD1 tBACD2
tBZD
A21-A0
Figure 19.7 Bus Release Timing
RENESAS 453
19.3.3
Bus Timing
Table 19.6 Bus Timing (1) Conditions: VCC = 5.0 V 10%, V SS = 0 V, = 20 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
RENESAS 454
Item Address delay time CS delay time 1 CS delay time 2 CS delay time 3 CS delay time 4 Access time 1*6 35% duty*2 from read strobe 50% duty Access time 35% from read strobe 2*6 duty *2
Symbol t AD t CSD1 t CSD2 t CSD3 t CSD4 t RDAC1
Min -- -- -- -- -- t cyc x 0.65 - 20 t cyc x 0.5 - 20 t cyc x (n+1.65) - 20 *3
Max 20*1 25 25 20 20 -- -- --
Unit Figures ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 19.8, 19.9, 19.11-19.15, 19.19, 19.24-19.28 19.8, 19.9, 19.11-19.14, 19.19 19.9, 19.13, 19.14, 19.19, 19.20 19.9, 19.13, 19.14, 19.19 19.11, 19.12 19.11, 19.12, 19.20 19.9, 19.13, 19.14, 19 19.11, 19.12 19.9, 19.11-19.14 19.19 19.9, 19.10 19.8 19.19 19.8, 19.9, 19.11-19.14, 19.19, 19.20 19.8, 19.9, 19.20
t RDAC2
50% duty Access time 3*6 35% duty *2 from read strobe 50% duty Read strobe delay time Read data setup time Read data hold time Write strobe delay time 1 Write strobe delay time 2 Write strobe delay time 3 Write strobe delay time 4 Write data delay time 1 Write data delay time 2 Write data hold time t RSD t RDS t RDH t WSD1 t WSD2 t WSD3 t WSD4 t WDD1 t WDD2 t WDH t RDAC3
t cyc x (n+1.5) - -- - 20 *3 t cyc x (n+0.65) - 20 *3 --
t cyc x (n+0.5) - -- - 20 *3 -- 15 0 -- -- -- -- -- -- 0 20 -- -- 20 20 20 20 35 20 --
RENESAS 455
Table 19.6 Bus Timing (1) (cont) Conditions: VCC = 5.0 V 10%, V SS = 0 V, = 20 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
Item Parity output delay time 1 Parity output delay time 2 Parity output hold time Wait setup time Wait hold time Read data access time Read data access time RAS delay time 1 RAS delay time 2 CAS delay time 1 CAS delay time 2 CAS delay time 3 Column address setup time Read data access time from CAS 1*6 35% duty *2 1*6 2*6 Symbol t WPDD1 t WPDD2 t WPDH t WTS t WTH t ACC1 t ACC2 t RASD1 t RASD2 t CASD1 t CASD2 t CASD3 t ASC t CAC1 Min -- -- 0 14 10 t cyc - 30* 4 t cyc x (n+2) - 30*3 -- -- -- -- -- 0 t cyc x 0.65 - 19 t cyc x 0.5 - 19 t CAC2 t RAC1 t RAC2 t CP t cyc x (n+1) - 25*3 t cyc x 1.5 - 20 Max 40 20 -- -- -- -- -- 20 30 20 20 20 -- -- -- -- -- Unit Figures ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 19.13, 19.14, 19.15 19.11, 19.12 19.13, 19.14, 19.15 19.12 19.8, 19.11, 19.12 19.9, 19.10, 19.13, 19.14 19.11-19.14, 19.16-19.18 19.11 19.13, 19.14, 19.16-19.18 19.11, 19.12 19.9, 19.13, 19.14 19.11, 19.12 19.9, 19.11-19.14 19.10, 19.15, 19.19
50% duty
Read data access time from CAS 2 *6 Read data access time from RAS 1 *6 Read data access time from RAS 2 *6 High-speed page mode CAS precharge time
t cyc x (n+2.5) - -- 20*3 t cyc x 0.25 --
RENESAS 456
Table 19.6 Bus Timing (1) (cont) Conditions: VCC = 5.0 V 10%, V SS = 0 V, = 20 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
Item AH delay time 1 AH delay time 2 Multiplexed address delay time Multiplexed address hold time DACK0, DACK1 delay time 1 DACK0, DACK1 delay time 2 DACK0, DACK1 delay time 3 DACK0, DACK1 delay time 4 DACK0, DACK1 delay time 5 Read delay time 35% duty *2 Symbol t AHD1 t AHD2 t MAD t MAH t DACD1 t DACD2 t DACD3 t DACD4 t DACD5 t RDD Min -- -- -- 0 -- -- -- -- -- -- -- t DS t CSR t RAH t WCH t WCS t ACP duty *2 0*5 10 10 15 0 0 Max 20 20 30 -- 23 23 20 20 20 t cyc x 0.35 + 12 t cyc x 0.5 + 15 -- -- -- -- -- -- Unit Figures ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 19.12 19.11 19.8, 19.9, 19.1119.15, 19.19, 19.2419.28 19.11, 19.13 19.16, 19.17, 19.18 19.11, 19.13 19.9, 19.13, 19.14, 19.19 19.11, 19.12 19.8, 19.9, 19.11- 19.14, 19.19, 19.20 19.19
50% duty Data setup time for CAS CAS setup time for RAS Row address hold time Write command hold time Write command setup time 35%
50% duty
Access time from CAS precharge *6 Notes: 1. 2. 3. 4. 5. 6.
t cyc -- - 20
HBS and LBS signals are 25 ns. When frequency is 10 MHz or more. n is the number of wait cycles. Access time from addresses A0 to A21 is tcyc-25. -5 ns for parity output of DRAM long-pitch access. It is not necessary to meet the tRDS specification as long as the access time specification is met.
RENESAS 457
Table 19.7 Bus Timing (2) Conditions: VCC = 5.0 V 10%, V SS = 0 V, = 16.6 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
Item Address delay time CS delay time 1 CS delay time 2 CS delay time 3 CS delay time 4 Access time 35% from read strobe 1*6 duty *2 Symbol t AD t CSD1 t CSD2 t CSD3 t CSD4 t RDAC1 Min -- -- -- -- -- Max 25*1 30 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 19.8, 19.9, 19.19 19.8, 19.9, 19.11-19.14, 19.19 19.9, 19.13, 19.14, 19.19, 19.20 19.9, 19.13, 19.14, 19.19 19.11, 19.12 19.11, 19.12, 19.20 19.9, 19.13, 19.14, 19.19 19.11, 19.12 19.9, 19.11-19.14 19.9, 19.13, 19.14 19.11, 19.12 19.9, 19.11-19.14 19.19 19.9, 19.10 19.8 19.19 Figures 19.8, 19.9, 19.11-19.14, 19.19, 19.20 19.8, 19.9, 19.20
t cyc x 0.65 - -- 20 t cyc x 0.5 - 20 -- -- -- -- -- 25 -- -- 25 25 25 25 45 25 -- 45 25 --
50% duty Access time 2*6 35% duty *2 from read strobe 50% duty Access time 3*6 35% duty *1 from read strobe 50% duty Read strobe delay time Read data setup time Read data hold time Write strobe delay time 1 Write strobe delay time 2 Write strobe delay time 3 Write strobe delay time 4 Write data delay time 1 Write data delay time 2 Write data hold time Parity output delay time 1 Parity output delay time 2 Parity output hold time t RSD t RDS t RDH t WSD1 t WSD2 t WSD3 t WSD4 t WDD1 t WDD2 t WDH t WPDD1 t WPDD2 t WPDH t RDAC3 t RDAC2
t cyc x (n + 1.65) - 20 *3 t cyc x (n + 1.5) - 20 *3 t cyc x (n + 0.65) - 20 *3 t cyc x (n + 0.5) - 20 *3 -- 15 0 -- -- -- -- -- -- 0 -- -- 0
RENESAS 458
Table 19.7 Bus Timing (2) (cont) Conditions: VCC = 5.0 V 10%, V SS = 0 V, = 16.6 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
Item Wait setup time Wait hold time Read data access time Read data access time RAS delay time 1 RAS delay time 2 CAS delay time 1 CAS delay time 2 CAS delay time 3 Column address setup time Read data access 35% time from CAS 1*6 duty *2 1*6 2*6 Symbol t WTS t WTH t ACC1 t ACC2 t RASD1 t RASD2 t CASD1 t CASD2 t CASD3 t ASC t CAC1 Min 19 10 t cyc - 30* 4 t cyc x (n+2) - 30*3 -- -- -- -- -- 0 t cyc x 0.65 - 19 t cyc x 0.5 - 19 t CAC2 t RAC1 t RAC2 t CP t AHD1 t AHD2 t MAD t MAH Max -- -- -- -- 25 35 25 25 25 -- -- -- Unit Figures ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 19.13, 19.14, 19.15 19.11, 19.12 19.13, 19.14, 19.15 19.12 19.19 19.8, 19.11, 19.12 19.9, 19.10, 19.13, 19.14 19.11-19.14, 19.16-19.18 19.11 19.13, 19.14, 19.16-19.18 19.11, 19.12 19.10, 19.15, 19.19
50% duty Read data access time from CAS 2 *6 Read data access time from RAS 1 *6 Read data access time from RAS 2 *6 High-speed page mode CAS precharge time AH delay time 1 AH delay time 2 Multiplexed address delay time Multiplexed address hold time
t cyc x (n + 1) - -- 25*3 t cyc x 1.5 - 20 --
t cyc x (n + 2.5) -- - 20 *3 t cyc x 0.25 -- -- -- 0 -- 25 25 30 --
RENESAS 459
Table 19.7 Bus Timing (2) (cont) Conditions: VCC = 5.0 V 10%, V SS = 0 V, = 16.6 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
Item DACK0, DACK1 delay time 1 DACK0, DACK1 delay time 2 DACK0, DACK1 delay time 3 DACK0, DACK1 delay time 4 DACK0, DACK1 delay time 5 Read delay time 35% duty *2 Symbol t DACD1 t DACD2 t DACD3 t DACD4 t DACD5 t RDD t DS t CSR t RAH t WCH t WCS t ACP duty *2 Min Max -- -- -- -- -- -- -- 0*5 10 10 15 0 0 25 25 25 25 25 t cyc x 0.5 + 15 -- -- -- -- -- -- Unit Figures ns ns ns ns ns 19.8, 19.9, 19.11-19.15, 19.19 19.11, 19.13 19.16, 19.17, 19.18 19.11, 19.13 19.8, 19.9, 19.11-19.14, 19.19, 19.20 19.9, 19.13, 19.14, 19.19 19.11, 19.12
t cyc x 0.35 + 12 ns ns ns ns ns ns ns ns ns
50% duty
Data setup time for CAS CAS setup time for RAS Row address hold time Write command hold time Write command 35% setup time 50% duty Access time from CAS precharge *6 Notes 1. 2. 3. 4. 5. 6.
19.11
t cyc -- -20
19.12
HBS and LBS signals are 30 ns. When frequency is 10 MHz or more n is the number of wait cycles. Access time from addresses A0 to A21 is tcyc-25. -5 ns for parity output of DRAM long-pitch access It is not necessary to meet the tRDS specification as long as the access time specification is met.
RENESAS 460
T1 CK tAD A21-A0 HBS, LBS tCSD1 CSn tRDD RD (Read) tACC1*2 tRDS AD15-AD0 DPH, DPL (Read) DACK0 DACK1 For t RDAC1 , use t cyc x 0.65 - 20 (for 35% duty) or t cyc x 0.5 - 20 (for 50% duty) instead of tcyc - t RDD - t RDS. For tACC1, use t cyc - 30 instead of t cyc - t AD (or tCSD1) - tRDS. t RDH is measured from A21-A0, CSn, or RD, whichever is negated first. tRDH*3 tRDAC1*1 tRSD tCSD2
tDACD1
tDACD2
Notes: 1. 2. 3.
Figure 19.8 Basic Bus Cycle: One-State Access
RENESAS 461
T1
T2
CK A21-A0 HBS, LBS
tAD
tCSD1 CSn tRDAC2*1
tCSD2
tRDD RD (Read)
tRSD
tACC2*2 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) WRH, WRL, WR (Write) tWDD1 AD15-AD0 (Write) tWPDD1 DPH, DPL (Write) tDACD3 DACK0 DACK1 (Write) tDACD3
tRDS
tRDH*3
tDACD1
tDACD2
tWSD1
tWSD2
tWDH
tWPDH
Notes: 1 2 3
For tRDAC2, use t cyc x (n + 1.65) - 20 (for 35% duty) or tcyc x (n + 1.5) - 20 (for 50% duty) instead of tcyc x (n + 2) - tRDD - tRDS. For tACC2, use t cyc x (n + 2) - 30 instead of tcyc x (n + 2) - tAD (or tCSD1) - tRDS. t RDH is measured from A21-A0, CSn, or RD, whichever is negated first.
Figure 19.9 Basic Bus Cycle: Two-State Access
RENESAS 462
T1
TW
T2
CK
A21-A0 HBS, LBS
CSn
tRDAC2*1 RD (Read) tACC2*2 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read)
WRH, WRL, WR (Write) AD15-AD0 DPH, DPL (Write) DACK0 DACK1 (Write) tWTS WAIT tWTH tWTS tWTH
Notes: 1. 2.
For tRDAC2, use t cyc x (n + 1.65) - 20 (for 35% duty) or tcyc x (n + 1.5) - 20 (for 50% duty) instead of tcyc x (n + 2) - tRDD - tRDS. For tACC2, use t cyc x (n + 2) - 30 instead of tcyc x (n + 2) - tAD (or tCSD1) - tRDS.
Figure 19.10 Basic Bus Cycle: Two States + Wait State
RENESAS 463
Tp CK tAD A21-A0
Tr
Tc
tAD Row tRASD1 tRAH tASC tDS tCASD1 Column tRASD2
RAS
CAS
RD(Read)
tRDD
tRSD tWCH tDACD1 tDACD2
WRH, WRL, (Read) DACK0 DACK1 (Read) tRAC1*3
tCAC1*1 tACC1*2 tRDS tRDH*4
AD15-AD0 DPH, DPL (Read)
RD(Write)
tWSD3
WRH, WRL, (Write) AD15-AD0 (Write) DPH, DPL (Write) DACK0 DACK1 (Write) tWPDD2
tWCS
tWSD4
tWDD2
tWDH
tWPDH
tDACD4 tDACD5
Notes: 1. 2. 3. 4.
For tCAC1, use t cyc x 0.65 - 19 (for 35% duty) or t cyc x 0.5 - 19 (for 50% duty) instead of tcyc - tAD - t ASC - tRDS. For tACC1, use t cyc - 30 instead of tcyc - tAD - t RDS. For tRAC1, use t cyc x 1.5 - 20 instead of t cyc x 1.5 - t RASD1 - tRDS. t RDH is measured from A21-A0, RAS, or CAS, whichever is negated first.
Figure 19.11 DRAM Bus Cycle (Short Pitch, Normal Mode)
RENESAS 464
Tp CK tAD A21-A0
Tr
Tc
Tc
Tc
Tc
tAD
Row address Column address Column address Column address Column address
tRASD1 RAS
tASC tCP
tRASD2
CAS
tRDD
RD(Read)
tRSD
WRH, WRL, WR(Read) tCAC1*1 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) tRAC1*3 tACC1*2
tACP
tRDS tRDH*4
tRDH*5
tDACD1 tDACD2
Notes: 1.
2.
3.
4. 5.
For tCAC1, use tcyc x 0.65 - 19 (for 35% duty) or t cyc x 0.5 - 19 (for 50% duty) instead of t cyc - t AD - t ASC - tRDS . It is not necessary to meet the tRDS specification as long as the t CAC1 specification is met. For tACC1, use tcyc - 30 instead of t cyc - t AD - t RDS . It is not necessary to meet the tRDS specification as long as the t ACC1 specification is met. For tRAC1, use tcyc x 1.5 - 20 instead of t cyc x 1.5 - t RASD1 - t RDS . It is not necessary to meet the tRDS specification as long as the t RAC1 specification is met. t RDH is measured from A21--A0 or CAS, whichever is negated first. t RDH is measured from A21--A0, RAS, or CAS, whichever is negated first.
Figure 19.12 (a) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Read)
RENESAS 465
Tp CK
tAD
Tr
Tc
Silent cycle
Tc
tAD
Row address Column address Column address
A21-A0 tRASD1 RAS
tRASD2
tASC CAS
RD (Write)
tWSD3
tWSD4
WRH, WRL, WR (Write)
tWDD2
tWDH
AD15-AD0 DPH, DPL (Write)
tWPDD2 tWPDH
DPH, DPL (Write)
tDACD4 tDACD5
DACK0 DACK1 (Write)
tDACD5
Figure 19.12 (b) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Write) Note: For details of the silent cycle, see section 8.5.5, Burst Operation.
RENESAS 466
Tp CK tAD A21-A0
Tr
Tc1
Tc2
tAD
Row tRAH
Column
tRASD2
tRASD1 RAS
tDS tCASD2 CAS RD(Read) WRH, WRL, (Read) AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) RD(Write) WRH, WRL, (Write) AD15-AD0 (Write) DPH, DPL (Write) DACK0 DACK1 (Write) tWSD1 tWSD2 tWDH tRAC2*
3
tCASD3
tRDD
tRSD
tWCH
tACC2*2
tCAC2
*1
tRDS tDACD2
tRDH*4
tDACD1
tWDD1 tWPDD1 tDACD3 tDACD3
tWPDH
Notes: 1. 2. 3. 4.
For tCAC2, use tcyc x (n + 1) - 25 instead of tcyc x (n + 1) - tCASD2 - tRDS. For tACC2 , use t cyc x (n + 2) - 30 instead of tcyc x (n + 2) - tAD - t RDS. For tRAC2, use t cyc x (n + 2.5) - 20 instead of tcyc x (n + 2.5) - tRASD1 - tRDS. t RDH is measured from A21-A0, CAS, or RAS, whichever is negated first.
Figure 19.13 DRAM Bus Cycle: (Long Pitch, Normal Mode)
RENESAS 467
Tp
CK
Tr tAD tAD Row tRASD1
Tc1
Tc2
Tc1
Tc2
A21-A0
Column
Column tRASD2
RAS
tCASD2
CAS RD(Read) WRH, WRL, (Read) AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) RD(Write) WRH, WRL, (Write) AD15-AD0 (Write)
tCASD3 tRSD
tCASD3
tRDD
tRAC2*3
tACC2*2
tCAC2*1 tRDS tRDH*4
tRDH*5
tDACD1
tDACD2
tDACD1
tDACD2
tWSD1
tWSD2
tWSD1
tWSD2
tWDD1 tWPDD1
tWDH tWDD1 tWPDH tWPDD1
tWDH tWPDH
DPH, DPL (Write) DACK0 DACK1 (Write)
tDACD3
tDACD3
tDACD3
tDACD3
Notes: 1. 2. 3. 4. 5.
For tCAC2, use t cyc x (n + 1) - 25 instead of tcyc x (n + 1) - tCASD2 - tRDS. For tACC2, use t cyc x (n + 2) - 30 instead of tcyc x (n + 2) - tAD - t RDS. For tRAC2, use t cyc x (n + 2.5) - 20 instead of tcyc x (n + 2.5) - tRASD1 - tRDS. t RDH is measured from A21-A0 or CAS, whichever is negated first. t RDH is measured from A21-A0, RAS, or CAS whichever is negated first.
Figure 19.14 DRAM Bus Cycle: (Long Pitch, High-Speed Page Mode)
RENESAS 468
Tp
CK A21-A0 RAS CAS RD(Read) WRH, WRL, (Read)
Tr
Tc1
Tw
Tc2
Row
Column tRSD tRDD
tCAC2*1 tACC2*2 tRAC2*3
AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) RD(Write) WRH, WRL, (Write) AD15-AD0 (Write) DPH, DPL (Write) DACK0 DACK1 (Write) WAIT
tWTS tWTH
tWTS tWTH
Notes: 1. 2. 3.
For tCAC2, use t cyc x (n + 1) - 25 instead of tcyc x (n + 1) - tCASD2 - tRDS. For tACC2, use t cyc x (n + 2) - 30 instead of tcyc x (n + 2) - tAD - t RDS. For tRAC2, use t cyc x (n + 2.5) - 20 instead of tcyc x (n + 2.5) - tRASD1 - tRDS.
Figure 19.15 DRAM Bus Cycle: (Long Pitch, High-Speed Page Mode + Wait State)
RENESAS 469
TRp
CK
TRr
TRc
tRASD1
RAS
tRASD2
tCSR tCASD2
CAS
tCASD3
WRH, WRL
Figure 19.16 CAS-before-RAS Refresh (Short Pitch)
TRp
TRr
TRc
TRc
CK
tRASD1 tRASD2
RAS
tCSR tCASD3 tCASD2
CAS
WRH, WRL
Figure 19.17 CAS-before-RAS Refresh (Long Pitch)
RENESAS 470
TRp
CK
TRr
TRc
TRcc
tRASD1
RAS
tRASD2
tCSR tCASD2
CAS
tCASD3
Figure 19.18 Self Refresh
RENESAS 471
T1 CK tAD A21-A0 HBS, LBS
T2
T3
T4
tCSD3 CS6 tAHD1 AH tRDD RD (Read) tMAD AD15-AD0 (Read) tMAH tRDAC3 tRSD tAHD2
tCSD4
tRDH
Address
tDACD1
Data (input)
tDACD2
DACK0 DACK1 (Read) WRH, WRL, WR (Write) tMAD AD15-AD0 (Write) tMAH
tWSD1
tWSD2
tWDD1
tWDH
Address
tDACD3
Data (output)
tDACD3
DACK0 DACK1 (Write) tWTS WAIT
tWTH
Figure 19.19 Address/Data Multiplex I/O Bus Cycle
RENESAS 472
T1 CK tAD A21-A0 HBS, LBS tCSD1 CSn tWSD1 WRH, WRL, WR (Write) tDACD1 DACK0 DACK1 (Write) tDACD2 tWSD4 tCSD2
Figure 19.20 DMA Single Transfer/1 State Access Write
RENESAS 473
Table 19.8 Bus Timing (3) Conditions: VCC = 3.0 to 5.5 V, VSS = 0 V, = 12.5 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
Item Address delay time CS delay time 1 CS delay time 2 CS delay time 3 CS delay time 4 Access time 35% from read strobe 50% duty Access time 35% from read strobe 50% duty Access time 35% from read strobe 50% duty Read strobe delay time Read data set-up time Read data hold time Write strobe delay time 1 Write strobe delay time 2 Write strobe delay time 3 Write strobe delay time 4 Write data delay time 1 Write data delay time 2 Write data hold time Parity output delay time 1 Parity output delay time 2 Parity output hold time 3*4 2*4 1*4 duty *1 duty *1 duty *1 Symbol Min t AD t CSD1 t CSD2 t CSD3 t CSD4 t RDAC1 t RDAC2 t RDAC3 t RSD t RDS t RDH t WSD1 t WSD2 t WSD3 t WSD4 t WDD1 t WDD2 t WDH t WPDD1 t WPDD2 t WPDH -- -- -- -- -- t cyc x 0.65 - 35 t cyc x 0.5 - 35 t cyc x (n+1.65) - t cyc x (n+1.5) - t cyc x (n+0.5) - -- 30 0 -- -- -- -- -- -- -10 -- -- -10 t cyc x (n+0.65) - 35*2 35*2 35*2 35*2 Max 40 40 40 40 40 -- -- -- -- -- -- 40 -- -- 40 30 40 40 70 40 -- 80 40 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 19.21, 19.22, 19.32 19.21, 19.22, 19.24-19.27, 19.32 19.22, 19.26, 19.27, 19.32, 19.33 19.22, 19.26, 19.27, 19.32 19.24, 19.25 19.24, 19.25, 19.33 19.22, 19.26, 19.27, 19.32 19.24, 19.25 19.22, 19.24-19.27, 19.32 19.22, 19.24, 19.27 19.24, 19.25 19.22, 19.24-19.27 19.32 19.22, 19.23 19.21, 19.32 Figures 19.21, 19.22, 19.24- 19.27, 19.32, 19.33 19.21, 19.22, 19.33
RENESAS 474
Table 19.8 Bus Timing (3) (cont) Conditions: VCC = 3.0 to 5.5 V, VSS = 0 V, = 12.5 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
Item Wait setup time Wait hold time Read data access time Read data access time RAS delay time 1 RAS delay time 2 CAS delay time 1 CAS delay time 2 CAS delay time 3 Column address setup time Read data 35% access time from 50% duty CAS 1*4 duty *1 1*4 2*4 Symbol Min t WTS t WTH t ACC1 t ACC2 t RASD1 t RASD2 t CASD1 t CASD2 t CASD3 t ASC t CAC1 40 10 t cyc - 44 t cyc x (n+2) - -- -- -- -- -- 0 t cyc x 0.65 - 35 t cyc x 0.5 - 35 t CAC2 t RAC1 t RAC2 t CP t AHD1 t AHD2 t MAD t MAH t cyc x (n+1) - 35*2 t cyc x 1.5 - 35 t cyc x (n+2.5) - 35*2 t cyc x 0.25 -- -- -- -10 44*2 Max -- -- -- -- 40 40 40 40 40 -- -- -- -- -- -- -- 40 40 40 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 19.26, 19.27, 19.28 19.24, 19.25 19.26, 19.27, 19.28 19.25 19.32 19.21, 19.24, 19.25 19.22, 19.23, 19.26, 19.28 19.24-19.27, 19.29- 19.31 19.24 19.26, 19.27, 19.29- 19.31 19.24, 19.25 Figures 19.23, 19.28, 19.32
Read data access time from CAS 2 *4 Read data access time from RAS 1 *4 Read data access time from RAS 2 *4 High-speed page mode CAS precharge time AH delay time 1 AH delay time 2 Multiplexed address delay time Multiplexed address hold time
RENESAS 475
Table 19.8 Bus Timing (3) (cont) Conditions: VCC = 3.0 to 5.5 V, VSS = 0 V, = 12.5 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products
Item Symbol Min Max -- -- -- -- -- -- -- t DS t CSR t RAH t WCH t WCS t WCS t ACP duty *1 0* 3 10 10 15 0 0 40 40 40 40 40 t cyc x 0.35 + 35 t cyc x 0.5 + 35 -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 19.25 19.24 19.21, 19.22, 19.2419.28, 19.32 19.24, 19.26 19.29-19.31 19.24, 19.26 Figures 19.21, 19.22, 19.24- 19.27, 19.32, 19.33 19.22, 19.26, 19.27, 19.32 19.24, 19.25
DACK0, DACK1 delay time 1 t DACD1 DACK0, DACK1 delay time 2 t DACD2 DACK0, DACK1 delay time 3 t DACD3 DACK0, DACK1 delay time 4 t DACD4 DACK0, DACK1 delay time 5 t DACD5 Read delay time 35% duty *1 t RDD 50% duty Data setup time for CAS CAS setup time for RAS Row address hold time Write command hold time Write command 35% setup time 50% duty Access time from CAS precharge *4 Notes: 1. 2. 3. 4.
tcyc -- -20
When frequency is 10 MHz or more. n is the number of wait cycles. -5 ns for parity output of DRAM long-pitch access It is not necessary to meet the tRDS specification as long as the access time specification is met.
RENESAS 476
T1 CK tAD A21-A0 HBS, LBS tCSD1 CSn tRDD RD (Read) tACC1*2 tRDS AD15-AD0 DPH, DPL (Read) DACK0 DACK1 For tRDAC1, use t cyc x 0.65 - 35 (for 35% duty) or t cyc x 0.5 - 35 (for 50% duty) instead of tcyc - tRDD - t RDS. For tACC1, use t cyc - 44 instead of tcyc - tAD (or tCSD1) - tRDS. t RDH is measured from A21-A0, CSn, or RD, whichever is negated first. tRDH*3 tRDAC1*1 tRSD tCSD2
tDACD1
tDACD2
Notes: 1. 2. 3.
Figure 19.21 Basic Bus Cycle: One-State Access
RENESAS 477
T1 CK tAD A21-A0 HBS, LBS tCSD1 CSn tRDD RD (Read) tACC2*2 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) tRDAC2*1
T2
tCSD2
tRSD
tRDS
tRDH*3
tDACD1
tDACD2
tWSD1
tWSD2
WRH, WRL, WR (Write) tWDD1 AD15-AD0 (Write) tWPDD1 DPH, DPL (Write) tDACD3 DACK0 DACK1 (Write) Notes: 1. 2. 3. For tRDAC2, use t cyc x (n + 1.65) - 35 (for 35% duty) or tcyc x (n + 1.5) - 35 (for 50% duty) instead of tcyc x (n + 2) - tRDD - tRDS. For tACC2, use t cyc x (n + 2) - 44 instead of tcyc x (n + 2) - tAD (or tCSD1) - tRDS. t RDH is measured from A21-A0, CSn, or RD, whichever is negated first. tDACD3 tWPDH tWDH
Figure 19.22 Basic Bus Cycle: Two-State Access
RENESAS 478
T1
TW
T2
CK
A21-A0 HBS, LBS
CSn
tRDAC2*1 RD (Read) tACC2*2 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) WRH, WRL, WR (Write) AD15-AD0 DPH, DPL (Write) DACK0 DACK1 (Write) tWTS WAIT Notes: 1. 2. For tRDAC2, use t cyc x (n + 1.65) - 35 (for 35% duty) or tcyc x (n + 1.5) - 35 (for 50% duty) instead of tcyc x (n + 2) - tRDD - tRDS. For tACC2, use t cyc x (n + 2) - 44 instead of tcyc x (n + 2) - tAD (or tCSD1) - tRDS. tWTH tWTS tWTH
Figure 19.23 Basic Bus Cycle: Two States + Wait State
RENESAS 479
Tp CK tAD A21-A0
Tr
Tc
tAD Row Column tRASD2 tDS tASC
tRASD1 RAS
tRAH
tCASD1 tRSD
CAS
RD(Read)
tRDD
tWCH WRH, WRL, (Read) DACK0 DACK1 (Read) tACC1*2 tRAC1*3 tCAC1*1 tRDS tRDH*4 tDACD1 tDACD2
AD15-AD0 DPH, DPL (Read)
RD(Write)
WRH, WRL, (Write) AD15-AD0 (Write)
tWSD3
tWCS
tWSD4 tWDH
tWDD2
DPH, DPL (Write) DACK0 DACK1 (Write)
tWPDD2
tWPDH
tDACD4 tDACD5
Notes: 1. 2. 3. 4.
For tCAC1, use t cyc x 0.65 - 35 (for 35% duty) or t cyc x 0.5 - 35 (for 50% duty) instead of tcyc - tAD - t ASC - tRDS. For tACC1, use t cyc - 44 instead of tcyc - tAD - t RDS. For tRAC1, use t cyc x 1.5 - 35 instead of t cyc x 1.5 - t RASD1 - tRDS. t RDH is measured from A21-A0, RAS, or CAS, whichever is negated first.
Figure 19.24 DRAM Bus Cycle (Short Pitch, Normal Mode)
RENESAS 480
Tp CK tAD A21-A0
Tr
Tc
Tc
Tc
Tc
tAD
Row address Column address Column address Column address Column address
tRASD1 RAS
tASC tCP
tRASD2
CAS
tRDD
RD(Read)
tRSD
WRH, WRL, WR(Read) tCAC1*1 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) tRAC1*3 tACC1*2
tACP
tRDS tRDH*4
tRDH*5
tDACD1 tDACD2
Notes: 1.
2.
3.
4. 5.
For tCAC1, use tcyc x 0.65 - 35 (for 35% duty) or t cyc x 0.5 - 35 (for 50% duty) instead of t cyc - t AD - t ASC - tRDS . It is not necessary to meet the tRDS specification as long as the t CAC1 specification is met. For tACC1, use tcyc - 44 instead of t cyc - t AD - t RDS . It is not necessary to meet the tRDS specification as long as the t ACC1 specification is met. For tRAC1, use tcyc x 1.5 - 35 instead of t cyc x 1.5 - t RASD1 - t RDS . It is not necessary to meet the tRDS specification as long as the t RAC1 specification is met. t RDH is measured from A21--A0 or CAS, whichever is negated first. t RDH is measured from A21--A0, RAS, or CAS, whichever is negated first.
Figure 19.25 (a) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Read)
RENESAS 481
Tp CK
tAD
Tr
Tc
Silent cycle
Tc
tAD
Row address Column address Column address
A21-A0
tRASD1 RAS tASC CAS
tRASD2
RD (Write)
tWSD3
tWSD4
WRH, WRL, WR (Write)
tWDD2
tWDH
AD15-AD0 DPH, DPL (Write)
tWPDD2 tWPDH
DPH, DPL (Write)
tDACD4 tDACD5
DACK0 DACK1 (Write)
tDACD5
Figure 19.25 (b) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Write) Note: For details of the silent cycle, see section 8.5.5, Burst Operation.
RENESAS 482
Tp CK tAD A21-A0
Tr
Tc1
Tc2
tAD Row tRAH Column
tRASD2
tRASD1 RAS
tCASD2 CAS RD(Read) WRH, WRL, (Read) AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) RD(Write) WRH, WRL, (Write) AD15-AD0 (Write) DPH, DPL (Write) DACK0 DACK1 (Write) tWSD1 tDACD1 tWCH
tDS
tCASD3
tRDD
tRDS
tCAC2*1 tACC2*2 tRAC2*3 tRDS tDACD2 tRDH*4
tWSD2 tWDH
tWDD1 tWPDD1 tDACD3 tDACD3
tWPDH
Notes: 1. 2. 3. 4.
For tCAC2, use t cyc x (n + 1) - 35 instead of tcyc x (n + 1) - tCASD2 - tRDS. For tACC2, use t cyc x (n + 2) - 44 instead of tcyc x (n + 2) - tAD - t RDS. For tRAC2, use t cyc x (n + 2.5) - 35 instead of tcyc x (n + 2.5) - tRASD1 - tRDS. t RDH is measured from A21-A0, CAS, or RAS, whichever is negated first.
Figure 19.26 DRAM Bus Cycle: (Long Pitch, Normal Mode)
RENESAS 483
Tp
CK
Tr tAD tAD Row tRASD1
Tc1
Tc2
Tc1
Tc2
A21-A0
Column
Column tRASD2
RAS
tCASD2
CAS RD(Read) WRH, WRL, (Read) AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) RD(Write) WRH, WRL, (Write) AD15-AD0 (Write)
tCASD3 tRSD
tCASD3
tRDD
tRAC2*3
tACC2*2
tCAC2*1 tRDS tRDH*4
tRDH*5
tDACD1
tDACD2
tDACD1
tDACD2
tWSD1
tWSD2
tWSD1
tWSD2
tWDD1 tWPDD1
tWDH tWDD1 tWPDH tWPDD1
tWDH tWPDH
DPH, DPL (Write) DACK0 DACK1 (Write)
tDACD3
tDACD3
tDACD3
tDACD3
Notes: 1. 2. 3. 4. 5.
For tCAC2, use t cyc x (n + 1) - 35 instead of tcyc x (n + 1) - tCASD2 - tRDS. For tACC2, use t cyc x (n + 2) - 44 instead of tcyc x (n + 2) - tAD - t RDS. For tRAC2, use t cyc x (n + 2.5) - 35 instead of tcyc x (n + 2.5) - tRASD1 - tRDS. t RDH is measured from A21-A0 or CAS, whichever is negated first. t RDH is measured from A21-A0, RAS, or CAS whichever is negated first.
Figure 19.27 DRAM Bus Cycle: (Long Pitch, High-Speed Page Mode)
RENESAS 484
Tp
CK A21-A0 RAS
Tr
Tc1
Tw
Tc2
Row
Column tRDS tRDD
CAS RD(Read) WRH, WRL, (Read)
tCAC2*1 tACC2*2 tRAC2*3
AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) RD(Write) WRH, WRL, (Write) AD15-AD0 (Write) DPH, DPL (Write) DACK0 DACK1 (Write) WAIT
tWTS tWTH
tWTS tWTH
Notes: 1. 2. 3.
For tCAC2, use t cyc x (n + 1) - 35 instead of tcyc x (n + 1) - tCASD2 - tRDS. For tACC2, use t cyc x (n + 2) - 44 instead of tcyc x (n + 2) - tAD - t RDS. For tRAC2, use t cyc x (n + 2.5) - 35 instead of tcyc x (n + 2.5) - tRASD1 - tRDS.
Figure 19.28 DRAM Bus Cycle: (Long Pitch, High-Speed Page Mode + Wait State)
RENESAS 485
TRp
CK
TRr
TRc
tRASD1
RAS
tRASD2
tCSR tCASD2
tCASD3
CAS
WRH, WRL
Figure 19.29 CAS-before-RAS Refresh (Short Pitch)
TRp
TRr
TRc
TRc
CK
tRASD1 tRASD2
RAS
tCSR tCASD3 tCASD2
CAS
WRH, WRL
Figure 19.30 CAS-before-RAS Refresh (Long Pitch)
RENESAS 486
TRp
CK
TRr
TRc
TRcc
tRASD1
RAS
tRASD2
tCSR tCASD2
tCASD3
CAS
Figure 19.31 Self Refresh
RENESAS 487
T1 CK tAD A21-A0 HBS, LBS
T2
T3
T4
tCSD3 CS6 tAHD1 AH tRDD RD (Read) tMAD AD15-AD0 (Read) tMAH tRDAC3 tRSD tAHD2
tCSD4
tRDH
Address
tDACD1
Data (input)
tDACD2
DACK0 DACK1 (Read) WRH, WRL, WR (Write) tMAD AD15-AD0 (Write) tMAH
tWSD1
tWSD2
tWDD1
tWDH
Address
tDACD3
Data (output)
tDACD3
DACK0 DACK1 (Write) tWTS WAIT
tWTH
Figure 19.32 Address/Data Multiplex I/O Bus Cycle
RENESAS 488
T1 CK tAD A21-A0 HBS, LBS tCSD1 CSn tWSD1 WRH, WRL, WR (Write) tDACD1 DACK0 DACK1 (Write) tDACD2 tWSD4 tCSD2
Figure 19.33 DMA Single Transfer/Single State Access Write
RENESAS 489
19.3.4
DMAC Timing
Table 19.9 DMAC Timing Case A: V CC = 3.0 to 5.5 V, VSS = 0 V, Ta = -20 to +75C* Case B: VCC = 5.0 V 10%, V SS = 0 V, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
Case A 12.5 MHz Item DREQ0, DREQ1 setup time DREQ0, DREQ1 hold time DREQ0, DREQ1 low level width Symbol Min t DRQS t DRQH t DRQW 80 30 1.5 Max -- -- -- Case B 16.6 MHz Min 40 30 1.5 Max -- -- -- 20 MHz Min 27 30 1.5 Max -- -- -- Unit ns ns t cyc 19.35 Figure 19.34
CK tDRQS DREQ0, DREQ1 level tDRQS DREQ0, DREQ1 edge tDRQS DREQ0, DREQ1 level release tDRQH
Figure 19.34 DREQ0, DREQ1 Input Timing (1)
CK DREQ0, DREQ1 edge tDRQW
Figure 19.35 DREQ0, DREQ1 Input Timing (2)
RENESAS 490
19.3.5
16-bit Integrated Timer Pulse Unit Timing
Table 19.10 16-bit Integrated Timer Pulse Unit Timing Case A: V CC = 3.0 to 5.5 V, VSS = 0 V, Ta = -20 to +75C* Case B: VCC = 5.0 V 10%, V SS = 0 V, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
Case A 12.5 MHz Item Output compare delay time Input capture setup time Timer clock input setup time Timer clock pulse width (single edge) Timer clock pulse width (both edges) Symbol t TOCD t TICS t TCKS t TCKWH/L t TCKWH/L Min -- 50 50 1.5 2.5 Max 100 -- -- -- -- 16.6 MHz Min -- 45 50 1.5 2.5 Max 100 -- -- -- -- Min -- 35 50 1.5 2.5 Case B 20 MHz Max 100 -- -- -- -- Unit ns ns ns t cyc t cyc 19.37 Figure 19.36
CK tTOCD Output compare*1 tTICS Output capture*2
Notes: 1. 2.
TIOCA0-TIOCA4, TIOCB0-TIOCB4, TOCXA4, TOCXB4 TIOCA0-TIOCA4, TIOCB0-TIOCB4
Figure 19.36 ITU Input/Output Timing
RENESAS 491
CK tTCKS TCLKA- TCLKD tTCKS
tTCKWL
tTCKWH
Figure 19.37 ITU Clock Input Timing
RENESAS 492
19.3.6
Programmable Timing Pattern Controller and I/O Port Timing
Table 19.11 Programmable Timing Pattern Controller and I/O Port Timing Case A: V CC = 3.0 to 5.5 V, VSS = 0 V, = 12.5 MHz, Ta = -20 to +75C* Case B: VCC = 5.0 V 10%, V SS = 0 V, = 16.6 MHz, Ta = -20 to +75C* Case C: VCC = 5.0 V 10%, V SS = 0 V, = 20 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
Cases A, B and C Item Port output delay time Port input hold time Port input setup time Symbol t PWD t PRH t PRS Min -- 50 50 Max 100 -- -- Unit ns ns ns Figure 19.38
T1
T2
T3
CK tPRS Ports A, B (read) Ports A, B (write) tPRH
tPWD
Figure 19.38 Programmable Timing Pattern Controller Output Timing
RENESAS 493
19.3.7
Watchdog Timer Timing
Table 19.12 Watchdog Timer Timing Case A: V CC = 3.0 to 5.5 V, VSS = 0 V, = 12.5 V, Ta = -20 to +75C* Case B: VCC = 5.0 V 10%, V SS = 0 V, = 16.6 MHz, Ta = -20 to +75C* Case C: VCC = 5.0 V 10%, V SS = 0 V, = 20 MHz, Ta = -20 to +75C* *: Normal products. Ta = -40 to +85C for wide-temperature range products.
Cases A, B and C Item WDTOVF delay time Symbol t WOVD Min -- Max 100 Unit ns Figure 20.39
CK tWOVD WDTOVF tWOVD
Figure 19.39 Watchdog Timer Output Timing
RENESAS 494
19.3.8
Serial Communications Interface Timing
Table 19.13 Serial Communications Interface Timing Case A: V CC = 3.0 to 5.5 V, VSS = 0 V, = 12.5 MHz, Ta = -20 to +75C* Case B: VCC = 5.0 V 10%, V SS = 0 V, = 16.6 MHz, Ta = -20 to +75C* Case C: VCC = 5.0 V 10%, V SS = 0 V, = 20 MHz, Ta = -20 to +75C* *: Normal products: Ta = -40 to +85C for wide-temperature range products.
Cases A, B and C Item Input clock cycle Input clock cycle (clocked synchronization) Input clock pulse width Input clock rise time Input clock fall time Transmission data delay time (clocked synchronization) Receive data setup time (clocked synchronization) Receive data hold time (clocked synchronization) Symbol t scyc t scyc t sckw t sckr t sckf t TXD t RXS t RXH Min 4 6 0.4 -- -- -- 100 100 Max -- -- 0.6 1.5 1.5 100 -- -- Unit t cyc t cyc t scyc t cyc t cyc ns ns ns 19.41 Figure 19.40
tSCKW
tSCKr
tSCKf
SCK0, SCK1 tscyc
Figure 19.40 Input Clock Timing
RENESAS 495
tscyc SCK0, SCK1 tTXD TxD0, TxD1 (transmission data) RxD0, RxD1 (reception data)
tRXS
tRXH
Figure 19.41 SCI I/O Timing (Clocked Synchronization Mode)
RENESAS 496
19.3.9
AC Characteristics Measurement Conditions
IOL
LSI output pin CL
Device under test output V Vref
IOH CL is set as follows for each pin. 30pF: CK, CASH, CASL, CS0-CS7, BREQ, BACK, AH, IRQOUT, RAS, DACK0, DACK1 50pF: A21-A0, AD15-AD0, DPH, DPL, RD, WRH, WRL, HBS, LBS, WR 70pF: All port outputs and peripheral module output pins other than the above. I OL and IOH values are as shown in section 19.2, DC Characteristics, and table 19.3, Permitted Output Current Values.
Figure 19.42 Output Load Circuit
RENESAS 497
19.4
Usage Note
The ZTAT version and the mask ROM version satisfy the electrical properties given in this document. However, effective values of the electrical properties, the operating margin, and the noise margin may differ with the manufacturing processes, on-chip ROM, and layout patterns. When conducting a system evaluation test using the ZTAT version, conduct a similar evaluation test of the mask ROM version before it replaces the ZTAT version.
RENESAS 498
SH7020, SH7021 Hardware Manual
Publication Date: 1st Edition, September 1994 3rd Edition, September 1998 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Group Hitachi, Ltd. Edited by: Technical Documentation Group UL Media Co., Ltd. Copyright (c) Hitachi, Ltd., 1994. All rights reserved. Printed in Japan.

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